Application guidelines

AN2846

14/35

Doc ID 15130 Rev 1

1.4.1

Input state register and parity bit generator

After filtering, the 8 input termination states are stored in an 8-bit input state register. Its

content is an image of the filtered input states in real time.

Figure 20.

Input state register and parity bit generator.

The SCLT3-8 has been designed to help diagnose incorrect data transmission. The four

parity bits generated by the parity bit generator are computed according to the input states

register content. They are updated each time the input state register content changes.

The parity bit 5 of PC1 register controls the 1 to 8 input data states; PC2-bit 4 controls inputs

5 to 8: PC3-bit 3 controls inputs 1 to 4;PC4-bit 2 controls inputs 3 to 6 according to the logic

equation:.

See example in Figure 21.

The decoding of all the parity bit results will help the microcontroller detect the possible

corrupted pair of bits occurring during the transmission.

Figure 21.

Parity bit generation example.

8 lines

Filtered

Input

states

http://www.mathcomposer.com

∑

=

=

odd.

if

0

even,

if

1

PC

n

INPUTstate

1N8

1N7

1N6

1N5

1N4

1N3

1N2

1N1

1

0

0

1

1

0

0

1

PC1

PC2

PC3

PC4

1

2

3

4

From

input

state

filter

From

input

state

filter

8 lines