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AN4505

First-in first-out (FIFO) buffer

6.3.4

Stream-to-FIFO mode

This mode is a combination of the Stream and FIFO modes previously described. In Stream-

to-FIFO mode, the FIFO buffer starts operating in Stream mode and switches to FIFO mode

when the selected interrupt occurs.

Follow these steps for Stream-to-FIFO mode configuration:

Configure desired interrupt generator using register INT1_CFG (0x30).

Turn on FIFO by setting the FIFO_EN bit to “1” in control register 5 (0x24). After this

operation the FIFO buffer is enabled but isn’t collecting data, output registers are

frozen to the last samples set loaded.

Activate Stream-to-FIFO mode by setting the FM[2:0] field to “011” in the FIFO control

The interrupt trigger is related to the IA bit in the INT1_SRC register and it is generated even

if the interrupt signal is not driven to an interrupt pad. A mode switch is performed if both the

IA and OVRN bits are set high. Stream-to-FIFO mode is sensitive to the trigger level and not

to the trigger edge which means that if Stream-to-FIFO is in FIFO mode and the interrupt

condition disappears, the FIFO buffer returns to Stream mode because the IA bit becomes

zero. It is recommended to latch the interrupt signal used as the FIFO trigger in order to

avoid losing interrupt events. If the selected interrupt is latched, the register INT1_SRC

must be read to clear the IA bit; after the read, the IA bit takes 2*ODR to go low.

In Stream mode the FIFO buffer continues filling, when the buffer is full, the OVRN bit is set

high and the next samples overwrite the oldest. When the trigger occurs, two different cases

can be observed:

If the FIFO buffer is already full (OVRN = “1”), it stops collecting data at the first sample

after trigger. FIFO content is composed of #30 samples collected before the trigger

event, the sample that has generated the interrupt event and one sample after the

trigger.

If FIFO isn’t yet full (initial transient), it continues filling until it is full (OVRN = “1”) and

then, if the trigger is still present, it stops collecting data.

Figure 21. Stream-to-FIFO mode: interrupt not latched

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