AN3119

Layout hints

Doc ID 16849 Rev 2

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Layout hints

The layout of any converter is a very important phase in the design process needing as

much attention by the design engineers as any other design phase. Even if it the layout

phase can sometimes look time consuming a good layout surely saves time during the

functional debugging and the qualification phases. Additionally, a power supply circuit with a

correct layout needs smaller EMI filters or less filter stages and so it allows a consistent

money saving.

Converters using the L6563S do not need any special or specific layout rule to be followed;

just the general layout rules for any power converter have to be applied carefully. Basic rules

are listed below; they can be used for other PFC circuits having any power level, working

either in transition mode or with a fixed-off time control.

1.

Keep power and signal RTN separated. Connect the return pins of the components

carrying high current such as input filters, sense resistors, or output capacitors, as

close as possible. This point is the RTN star point. A downstream converter must be

connected to this return point.

2.

Minimize the length of the traces relevant to the boost inductor, MOSFET drain, boost

rectifier and output capacitor.

3.

Keep signal components as close as possible to each L6563S relevant pin. To be more

precise, keep the tracks relevant to the pin #1 (INV) net as short as possible.

Components and traces relevant to the Error Amplifier have to be placed far from traces

and connections carrying signals with high dV/dt, such as the MOSFET drain. For high

power converters or very compact PCB layout a 10 nF capacitor connected to pin #9

(PWM_LATCH) and pin #12 (GND) might be required to decrease the noise picked up

by this pin while it is in its high impedance status.

4.

Please connect heat sinks to power GND.

5.

Add an external shield to the boost inductor and connect it to power GND.

6.

Please connect the RTN of signal components including the feedback, PFC_OK, and

MULT dividers close to the L6563S pin #12 (GND).

7.

Connect a ceramic capacitor (100÷470 nF) to pin #14 (Vcc) and pin #12 (GND), close

to the L6563S. Connect this point to the RTN star point (see rule 1).

Figure 37.

EVL6563S-250W TM PFC: PCB layout (SMT side view)