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AN2960 датащи(PDF) 32 Page - STMicroelectronics

номер детали AN2960
подробное описание детали  ultra compact linear accelerometer
PDF  41 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2960 датащи(HTML) 32 Page - STMicroelectronics

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Application information
AN2960
32/41
Doc ID 15557 Rev 1
9
Application information
9.1
Start-up sequence
Once the device is powered up, it automatically downloads the calibration coefficients from
the embedded Flash to the internal registers. When the boot procedure is complete (after
approximately 3 ms) the device automatically enters power-down mode.
To turn-on the device and gather acceleration data, it is necessary to write 47h in the
CTRL_REG1. With this command the three acceleration channels (i.e. X, Y and Z-axis) are
enabled and the output data rate is set to 100 Hz.
9.2
Reading acceleration data
9.2.1
Using the status register
The device is provided with a STATUS_REG which should be polled to check when a new
set of data is available. The reading procedure should be the following:
The check performed at step 3 permits understanding of whether the reading rate is
adequate compared to the data production rate. In case one or more acceleration samples
have been overwritten by new data because of a too slow reading rate, the bit
STATUS_REG(7) is set to 1.
The overrun bits are automatically cleared when all the data present inside the device have
been read and new data have not been produced in the meantime.
9.2.2
Using the DataReady signal
The device may be configured to generate one HW signal (DataReady) on either pin 9 or 11,
to flag that a new set of measurement data is available for reading. This signal corresponds
to the ZYXDA bit present in the STATUS_REG. The polarity of the signal is defined through
the IHL bit present in CTRL_REG3 and is deasserted when the acceleration data of all the
enabled channels have been read. To enable the DataReady signal on pin 11
(corresponding to INT1), it is necessary to set the I1CFG[2:0] bit present in CTRL_REG3 to
100. Conversely, to enable the DataReady signal on pin 9 (corresponding to INT2) it is
necessary to set the I2CFG[2:0] bit present in the CTRL_REG3 to 100.
1
read STATUS_REG
2
if STATUS_REG(3)=0 then goto 1
3
if STATUS_REG(7)=1 then some data have been overwritten
4
read OUTX
5
read OUTY
6
read OUTZ
7
data processing
8
goto 1



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