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AN2782 датащи(PDF) 17 Page - STMicroelectronics |
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AN2782 датащи(HTML) 17 Page - STMicroelectronics |
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17 / 39 page ![]() AN2782 Designing a fixed off-time PFC Doc ID 14763 Rev 2 17/39 In general, the capacitive losses are given by: where Cd is the total drain capacitance including the MOSFET and the other parasitic capacitances such as inductor etc. At the drain node, VMOS is the drain voltage at MOSFET turn-on. Taking into account the frequency variation with the input line voltage and the phase angle similar to (45), a detailed description of the capacitive losses per 1 nF of total drain capacitance can be calculated as: The total drain capacitance of the two MOSFETs is //Cd = 0.36 nF, Vout is the drain voltage at MOSFET turn-on. The function of the total losses of the input mains voltage is the sum of the three previous losses from equations (43), (45) and (47) multiplied for the two parallel MOSFET parameters: From (48) using the data relevant to the MOSFET selected and calculating the losses at VACmin and VACmax, we observe that the maximum total losses occurs at VACmin which is 9 W. From this number and the maximum ambient temperature (20), the total maximum thermal resistance required to keep the junction temperature below 125 °C is: If the result of equation (49) is lower than the junction-ambient thermal resistance given in the MOSFET datasheet for the selected device package, a heat sink must be used. (46) (47) (48) (49) ) VAC ( f V C 2 1 ) VAC ( P sw MOS 2 d cap ⋅ ⋅ ⋅ = () ϑ ⋅ ϑ π ⋅ = ′ ∫ π d ) , VAC ( f V 1 2 1 ) VAC ( P 0 sw 2 out cap ) VAC ( P C ) VAC ( P 2 t t ) VAC ( P RDS ) VAC ( P cap d sw fall rise cond on loss ′ ⋅ + ′ ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + + ′ ⋅ = ) VAC ( P T C 125 R loss ambx th − ° = W C 1 . 8 W 9 C 50 C 125 R th ° = ° − ° = |
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