UPD17072 datasheet(39/226 Pages) NEC

39 / 226 page

µPD17072,17073

6.2 Address Creation of General Register with Each Instruction

The following paragraphs 6.2.1 and 6.2.2 describe how the address of the general register is created when each

instruction is executed.

For details of the operation of each instruction, refer to 7. ALU (Arithmetic Logic Unit) BLOCK.

6.2.1 Addition (“ADD r, m”, “ADDC r, m”),

subtraction (“SUB r, m”, “SUBC r, m”),

logical operation (“AND r, m”, “OR r, m”, “XOR r, m”),

direct transfer (“LD r, m”, “ST m, r”),

rotate processing (“RORC r”) instructions

Table 6-1 shows the address of general register “R” specified by an instruction operand “r”. The operand “r”

specifies only the column address.

Table 6-1. Address Creation of General Register

6.3 Notes on Using General Register

There is no instruction available that performs an operation between the general register and immediate data.

To perform an operation between the data memory specified as the general register and immediate data, the data

memory must be treated as data memory instead of as the general register.

Bank

Row address

Column address

General register address

Fixed to 0

Fixed to 1

6.2.2 Indirect transfer (“MOV @r, m”, “MOV m, @r”) instructions

Table 6-2 shows the address of the general register “R” specified by instruction operand “r”, and the indirect transfer

address specified by “@R”.

Table 6-2. Address Creation of General Register

Bank

Row address

Column address

General register address

Fixed to 0

Indirect transfer address

Contents of R

Fixed to 0

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