2.1-channel applications using two devices

AN4569

14/29

DocID026803 Rev 1

3.1.1

Component selection

The selection of components is a key factor for the cost of the whole application.

The following list includes components grouped according to different sections of the

schematic:



Decoupling capacitors on VDD_DIG and PLL_VDD pins are 100 nF low voltage;



Decoupling capacitors on VCC pins (100 nF, 1 μF and 100 μF) must be aligned with the

external power supply used. If 24 V is used, the rate for the capacitors must be 35 V;



Decoupling capacitors on the internal regulator (C6S, C6M, C7S, C7M and C14M in

the schematic) can have a low-voltage rate. This because they are 3.3 V regulators;



Coil saturation current must be compatible with the peak current of the application.

3.1.2

Decoupling capacitors

Figure 12. Schematics for decoupling

The decoupling capacitors on high-voltages pins, (C21S/M, C22 S/M, C23 S/M and C24

S/M) must be placed as close as possible to the VCC pins. This is in order to avoid parasitic