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AN4092 датащи(PDF) 14 Page - STMicroelectronics |
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AN4092 датащи(HTML) 14 Page - STMicroelectronics |
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14 / 38 page ![]() Power Management Controller (PMC) AN4092 14/38 Doc ID 023080 Rev 2 For EMC reasons, decoupling capacitors are connected to the VDD and VSS of adjacent pins. This is illustrated by Figure 6. Figure 6. Implementation of decoupling Capacitors Do not place one or more caps close to the transistor emitter in order to avoid potential resonant CLC network (emitter cap(s) -> parasitic inductance -> VDD caps). 1.2 External power supply configuration In this configuration the three voltage levels required are provided externally: VRCCTL can be left floating, VRC33 becomes the input of the 3.3 voltage and VDD pins/balls must be connected to the 1.2 V source. In order to switch off the internal 3.3 voltage regulator, two solutions are possible: 1. VDDREG = GND Disabling the regulator using this option implies disabling also the Low Voltage Inhibit circuit. SPC564Axx 2. vrc3p3_shutdown_shadow_bit = 0 (bit 31, least significant bit) in the FLASH_BIU4 register (0xC3F8_802C)(g) The default value after reset of the volatile register FLASH_BIU4 can be modified by programming the shadow FLASH location 0x00FF_FE10. SPC563Mxx 3. V33EN = 0 g. The internal 3.3 V regulator is always switched on during reset. |
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