AN4092

Power Management Controller (PMC)

Doc ID 023080 Rev 2

7/38

3.3V regulator is intended for internally operation only (oscillator, part of FLASH, some

Nexus pins) and it must not be used to supply external circuitry or other IOs. Nevertheless,

VRC33 can be used as the reference on the debug connector of the JTAG/Nexus

Please notice that the JTAG and some Nexus signals (TCK, TDI, TDO, TMS, JCOMP,

MSEO[0:1], RDY, MDO[4..11], EVTO, EVTI) even if powered by a nominal 5V supply,

VDDEH7, are always operating on 3.3 voltage levels, being MultiV pads configured by

default (this setting cannot be changed) in low swing mode. On the other hand, when the

same MultiV pads are configured as GPIO (or eTPU), they work on 5V levels (this setting

cannot be changed either).

1.1.3

1.2V power supply and regulator controller

Most of the internal device circuitry is powered by the 1.2 V VDD input. This includes the

core and the majority of the device internal logic. An internal regulator controller is

implemented to provide a more cost optimized solution. By using an external ballast

transistor, the power loss from reducing the 5 V to 1.2 V can be dissipated externally.

This 1.2V voltage regulator controller provides a current signal (VRCCTL) that drives the

base of the external transistor. VDD is internally connected to the a sense signal that is

compared to an internal bandgap reference that sets the reference voltage. Depending on

VDD the current flowing out of the VRCCTL is adjusted to keep the 1.2 voltage level.

1.1.4

External ballast transistor

The following NPN transistors are guaranteed for use with the on-chip voltage regulator

controller: ON Semiconductor BCP68T1 or NJD2873 as well as NXP BCP68. The collector

of the external transistor is preferably connected to the same voltage supply source as the

output stage of the regulator, however it can also be connected to another voltage supply

(for example 3.3 V).

Any other transistor type / vendor may not work with the circuitry proposed in the

Section 1.1.5: 1.2V core regulator external circuitry in all the conditions, considering the

PVT (Process, Voltage, Temperature) worst cases.

Gain

The maximum current available or the VDD supply depends on the gain of the NPN

transistor used, it should be high enough to allow the operation in the worst case scenario in

terms of current consumption, given the minimum current that can be sourced by

From the SPC564Axx point of view, the worst case is at hot, the device may require up to

b.

IEEE-ISTO 5001™ - 2003 extract: “The VREF signal is used to establish the signaling levels of the debug

interface of the target system. Any current drawn from this pin should be limited to that needed for voltage

translation and/or signal interpolation and is not intended to supply logic functions or power. VREF is not

necessarily at the target processor VDD level.”

c.

Please refer to device DS.

d.

Preliminary data. Check the latest DS for updated figures.