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AN4276 датащи(PDF) 12 Page - STMicroelectronics

номер детали AN4276
подробное описание детали  ECC management on SPC560x
PDF  21 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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AN4276 датащи(HTML) 12 Page - STMicroelectronics

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ECC exception handling
AN4276
12/21
DocID024408 Rev 2
4.1
RAM ECC error action
It is up to the system requirements what to do in case of non-correctable ECC error during
read access to RAM memory. Handler can decide upon analysis of additional ECSM
registers, like ECSM.REAR register determining RAM address. If the application considers
such event as critical it is up to the application to terminate the system in the managed way.
To clear non-correctable ECC error in the memory means to overwrite whole 32-bit word of
affected RAM cell with a new value that refreshes data and ECC value.
4.2
Code Flash ECC error action
Criticality of non-correctable ECC error from Code Flash memory depends on type of the
access. Error during the instruction fetch represents critical situation and can be taken as
critical event requiring system termination.
ECC error during data access can or cannot represent critical event depending on system
implementation, like data redundancy etc. In such case error action depends on system
design.
4.3
Data Flash ECC error action
Non-correctable ECC exception coming from data Flash accesses can happen regularly
and may not represent critical events especially when data Flash memory is used for
EEPROM emulation. In such case it is desired to continue the program operation and let
application software to solve the ECC data error.
In principle there are two scenarios how error handler, IVOR2 in this case, can let
application software to continue its flow.
•
Continue with successive instruction of the read function
•
Continue from known address in the read function
Both scenarios are based on SRR0 register modification which changes effective address
where to continue once the handler returns back by rfi instruction. Modification of SRR0
register is necessary because it is loaded by effective address of the instruction that caused
the exception, which means that using the original value of SRR0 would cause execution of
the same instruction accessing corrupted memory cell once returning from the handler.
4.3.1
Continue with successive instruction of the read function
Target is to continue with the instruction that follows the instruction reading the data from
Flash memory like in Figure 5.



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