DocID024408 Rev 2

11/21

AN4276

ECC exception handling

4

ECC exception handling

As seen above, microcontroller always generates one of the exceptions for non-correctable

ECC errors depending on the EE and ME bits setting in the MSR register. Proper software

handlers should be placed on IVOR2, IVOR3 and IVOR1 exception vectors.

Z0 core used on SPC560x microcontrollers adds additional complexity to the exception

handling mixing several different exception causes to one vector, which means that software

handler has to find the reason of the interrupt first. IVOR2 and IVOR3 exceptions merge

following causes

•

ECC non-correctable errors (IVOR2 and IVOR3)

•

MPU access faults (IVOR2 and IVOR3)

•

Register protection violation (IVOR2)

General software flow of the exception handler IVOR2 and IVOR3 with focus on ECC

processing is shown in Figure 4. IVOR1 can differ in a way that having this exception

(machine check) means that system recovery is hardly possible and system should safely

terminate.

Figure 4. General IVOR2/3 handler software flow

IVOR 2/3 handler start

Read ECSM.ESR register

RNCE or FNCE

Return back and continue

to check other exception

reasons

RAM or Flash memory

Read ECSM.FEAR register

Code or Data flash

Return back and finish

exception handler.

Clear ECSM.FNCE flag

Clear ECSM.RNCE flag

NO

YES

FLASH

RAM

CODE

DATA

Take appropriate Code flash

ECC error action

(Most probably safe system

termination)

Take appropriate Data flash

ECC error action.

(Most probably report this

error and continue in system

operations)

Take appropriate RAM ECC

error action.

(Most probably safe system

termination in case of fault in

used RAM area)