UPD16675AP datasheet(7/36 Pages) NEC

7 / 36 page

µµµµPD16675A

1.2

Logic System (Continued)

Pin Symbol

Pin Name

Pin No.

I/O

Description

D0/DATA

Data bus/data

218

I/O

In parallel interface mode, this pin becomes the D0

bit of the data bus.

In serial interface mode, it becomes the input/output

pin of the command and display data (3 states).

D1 to D5

Data bus

217 to 213

I/O

In parallel interface mode, these pins become the D1

to D5 bits of the data bus.

In serial interface mode, leave them open.

D6/CAE

Data bus/chip

address enable

212

I/O

In 8-bit parallel interface mode, this pin becomes the

D6 bit of the data bus.

In 4-bit parallel interface and serial interface modes,

it becomes chip address enable. Also, at High level,

it becomes chip address valid; at Low level, chip

address invalid.

In 8-bit parallel interface, it becomes chip address

valid.

D7/NS

Data bus/nibble select

211

I/O

When the word select (WS) is High level, this bit

becomes the D7 bit of the data bus.

When WS is Low level, it becomes the nibble select

(NS). When NS is High level, it becomes 4-bit

parallel interface. When NS is Low level, it becomes

serial interface.

In 4-bit parallel interface mode, data cannot be read

out.

_____________

RESET

Reset

210

At Low level, internal initialization is performed.

VCHA

Boosting magnitude

switching

205

The boosting magnitude of the internal booster

circuit is switched over. At High level, it is switched

to 3X, while, at Low level, 2X.

DACHA

D/A converter

switching

202

Select whether to use the internal D/A converter for

temperature correction or not. At High level, this

circuit is used, at Low level, unused.

VEXT

Reference supply

switching

198

Selects the method for supplying the reference

power circuit. At High level, the circuit is supplied

externally; and, at Low level, internally.

SYNC

Synchronization

227

I/O

Input/output pin for synchronization.

Master mode: Output

Slave mode: Input

CS0 to CS2

Chip select

207 to 209

When used for multiple chips, these pins are used to

specify their addresses. They can be accessed only

when coinciding with b2 to b4 bits of the interface

control register.

OSCIN

Oscillation pin

200

OSCOUT

201

These pins are connected with the 1 M

Ω resistor.

When using external oscillation, input it into the

OSCIN, leaving the OSCOUT open.

OSCBRI

External clock for

blinks

199

Input pin of the 2-Hz external clock.

It internally divides this clock by 2 to generate 1 Hz

and make it the synchronizing signal for blinks.

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