UPD16675AP datasheet(6/36 Pages) NEC

6 / 36 page

µµµµPD16675A

PIN FUNCTIONS

1.1

Power System

Pin Symbol

Pin Name

Pin No.

I/O

Description

VDD1

Logic power supply

203,

204,

224

---

Power supply pin for logic

VDD2

Power supply pin for

booster circuit

197

---

Power supply pin for booster circuit. Set the pin to

VDD1

≤ VDD2.

VSS

Logic ground pin

206,

221,

222

---

Ground pin for logic

VLCD

Driver power supply

180, 181

---

Driver power supply pin. Output pin of internal

booster circuit. Connect with a 1-

µF booster

capacitor to the VDD2 pin.

When not using the internal booster circuit, the

driver power can be turned on directly.

VLC1 to VLC5

Driver reference

power supply

179 to 175

---

Reference power supply pin for LCD drive. When

the internal bias is selected, be sure to leave it open.

C1+, C1−,

C2+, C2−

Capacitor connection

pins

185 to 196

---

Capacitor connection pins for booster circuit.

Connect a 1

µF capacitor.

VEE

Driver ground pin

228, 229

---

Ground pin for driver

1.2

Logic System

Pin Symbol

Pin Name

Pin No.

I/O

Description

Word length selection

223

This pin selects the word length. At High level, it

becomes an 8-bit parallel interface. At Low level, it

becomes a 4-bit parallel interface if D7/NS is High;

and a serial interface if D7/NS is Low. When the

word length is 4 bits, data is transferred in the upper-

to-lower sequence by means of data buses D0 to D3.

The word length cannot be changed after power-on.

STB

Strobe

220

Data can be input/output at Low level either in

parallel interface or serial interface mode.

E/SCK

Enable/shift clock

219

In parallel interface mode, this becomes the data

enable input pin. During read-in, data is fetched into

the interface buffer at the rising edge. During read-

out, data is fetched from the interface buffer at the

falling edge.

In serial interface mode, this pin becomes the data

shift clock. During read-in, data is fetched into the

shift register at the rising edge. During read-out,

data is fetched from the shift register at the falling

edge.

CLKOUT

Clock for slave IC

output

226

This pin outputs an inverted oscillation clock. It

connects to slave IC’s OSCIN directly.

POCOUT

Power-on reset

monitor

225

Monitor pin for internal power-on reset.

At Low level, power-on reset is set internally. At

Low level, power-on reset is released.

The pin is for IC testing. Normally leave it open.

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