ADN2811

Rev. B | Page 17 of 20

CHOOSING AC-COUPLING CAPACITORS

The choice of ac-coupling capacitors at the input (PIN, NIN)

and output (DATAOUTP, DATAOUTN) of the ADN2811 must

be chosen carefully. When choosing the capacitors, the time

constant formed with the two 50 Ω resistors in the signal path

must be considered. When a large number of consecutive

identical digits (CIDs) are applied, the capacitor voltage can

drop due to baseline wander (see Figure 22), causing pattern

dependent jitter (PDJ).

For the ADN2811 to work robustly at OC-48, a minimum

capacitor of 0.1 µF to PIN/NIN and 0.1 µF on DATAOUTP/

DATAOUTN should be used. This is based on the assumption

that 1000 CIDs must be tolerated and that the PDJ should be

limited to 0.01 UI p-p.

50

Ω

ADN2811

NIN

PIN

50

Ω

V2

V1

V2b

V1b

TIA

LIMAMP

CDR

DATAOUTP

DATAOUTN

+

4

3

2

1

V1

V1b

V2

V2b

VTH = ADN2811 QUANTIZER THRESHOLD

VTH

NOTES

1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.

WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.

3. WHEN THE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS,

CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON

THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE.

4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2811. THE QUANTIZER WILL BE

ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.

Figure 22. Example of Baseline Wander