14

FCLK/SCLK Uncertainty Region

Figure 13 shows a clocking relationship for the HSP43124

Serial I/O filter that could result in an uncertainty at the

output. For simplicity, the frequency of FCLK and SCLK are

assumed to be equal to each other, and CLKOUT is

assumed to be equal to FLCK. When the rising edge of

FCLK lags behind the rising edge of SCLK by a small

samples are read into the filter compute engine is

determined by a race condition. In order to insure proper

3.8ns.

If exact timing (a particular clock edge for a specific data bit)

then make SCLK and FCLK synchronous. If FCLK and

SCLK are asynchronous, there will be jitter (a specific data

bit will be output as 1 of 2 possible clock edges depending

on the FCLK to SCLK phasing). For multiple part

applications, use synchronous clocks or use separate syncs

on what receives each data, as the outputs may vary by a

clock cycle.

Asynchronous FCLK and SCLK

If FCLK and SCLK are asynchronous clocks, then the output

sample rate (tracked by SYNCOUT) of the HSP43124 might

jitter in a real time system. This jitter will be demonstrated

using an SCLK with a period that is 3/2 times the period of

and Figure 14B. If the LSB occurs when there are two FCLK

edges in one SCLK period (see Figure 14A), then a null data

bit will occur in the DOUT data stream. If the LSB occurs

when there is one FCLK edge in one SCLK period for the

LSB (see Figure 14B), then no null data bit will occur. Given

the 3/2 period relationship between FCLK and SCLK, the

user can see that the SYNCOUT jitters by one clock. For

example, if the output data is represent by 16 bits, then the

number of CLKOUT rising edges between SYNCOUT pulses

should jitter between 15 and 16.

The SYNCOUT jitter demonstrated by the 3/2 frequency

example can be generalized to other asynchronous

SCLK at integer multiples of one another eliminates timing

jitter in the output sample rate.

SCLK

SYNCIN

DIN

FCLK

SYNCOUT

DOUT

MSB

MSB

LSB

LSB

MSB

MSB

FIGURE 13. FCLK/SCLK UNCERTAINTY REGION

FIGURE 14A. NUMBER OF CLKOUT = NUMBER OF BITS + 1

FOR THE TIME PERIOD BETWEEN SYNCOUTS

FIGURE 14B. NUMBER OF CLKOUT = NUMBER OF BITS FOR

THE TIME PERIOD BETWEEN SYNCOUTS

SCLK

SYNCIN

DIN

CLKOUT

SYNCOUT

DOUT

MSB

MSB

LSB

NULL

MSB

LSB

MSB

1

2

1

2

SCLK

SYNCIN

DIN

CLKOUT

SYNCOUT

DOUT

MSB

MSB

MSB

MSB

LSB

LSB

1

2

1

2

HSP43124