10

The coefficient set for each of the halfband filters is given in

Table 4. These values are the 32-bit, two’s complement,

integer representation of the filter coefficients. Scaling these

coefficients used to achieve unity gain in the Filter Processor.

If a specific frequency response is desired, a programmable

FIR filter may be activated. The filter compute engine takes

advantage of symmetry in FIR coefficients is by summing

data samples sharing a common coefficient prior to

multiplication. In this manner, two filter taps are calculated

per multiply accumulate cycle. If an asymmetric filter is

specified, only one tap per multiply accumulate cycle is

calculated.

The processing rate of the Filter Compute Engine is

proportional to FCLK. As a result, the frequency of FCLK

must exceed a minimum value to insure that a filter

calculation is complete before the result is required for

output. In configurations which do not use decimation, one

input sample period is available for filter calculation before

an output is required. For configurations which employ

decimation, up to 256 input sample periods may be available

for filter calculation. The following equation specifies the

minimum FCLK rate required for configurations which use

the programmable filter as an FIR filter.

SER word), TAPS is the number of taps in the FIR filter (0 to

number of halfband filters in the configuration (see Table 5),

cascade of halfband filters (see Table 5). For example, if the

input sample rate is 800kHz, a 128 tap FIR filter with no

decimation is selected, and a cascade of 2 halfband filters is

used, calculate the minimum FCLK rate as follows:

Thus, the Min FCLK is 19.6MHz.

NOTE: For configurations in which the halfband filters are used,

The longest length FIR filter realizable for a particular

configuration is determined by solving the above equation for

TAPS. The resulting expression is given below.

The maximum throughput sample rate may be specified by

NOTE: For configurations using filters with asymmetric coeffi-

cients, the term TAPS in the above equations should be multi-

plied by two in order to determine the correct FCLK.

The Filter Compute Engine is synchronized with an incoming

data stream by asserting the FSYNC input. When this input

is sampled low by the rising edge of FCLK, the Compute

Engine is reset, and the data word following the next

assertion of SYNCIN is recognized as the first data sample

input to the filter structure.

Min FCLK

F

S

DEC

HB

--------------------

TAPS/(2*DEC

HB

CLKS

1

++

()

or at least14F











=

(EQ. 2)

(EQ. 3)

Min FCLK

800kHz

4

---------------------



 128

2

1

----------



 33 1

++





200kHz

() 64 33 1

++

[] 19.6MHz

=

or at least 14 (800kHz)

11.2MHz

=















=

(EQ. 4)

TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS

NORMALIZED

FREQUENCY

HALFBAND

#1

HALFBAND

#2

HALFBAND

#3

HALFBAND

#4

HALFBAND

#5

0.000000

-0.000000

0.000000

0.000000

-0.000000

-0.000000

0.007812

0.000000

-0.000000

-0.000000

-0.000000

-0.000000

0.015625

-0.000113

-0.000000

-0.000000

-0.000000

-0.000000

0.023438

-0.000677

-0.000006

-0.000000

-0.000000

-0.000000

0.031250

-0.002243

-0.000052

-0.000000

-0.000000

-0.000000

0.039062

-0.005569

-0.000227

-0.000000

-0.000000

0.000000

0.046875

-0.011596

-0.000719

-0.000001

0.000000

-0.000000

0.054688

-0.021433

-0.001859

-0.000009

-0.000000

-0.000000

0.062500

-0.036333

-0.004165

-0.000041

-0.000000

-0.000000

0.070312

-0.057670

-0.008391

-0.000149

-0.000001

-0.000000

0.078125

-0.086916

-0.015557

-0.000448

-0.000012

-0.000000

0.085938

-0.125619

-0.026983

-0.001175

-0.000066

-0.000000

0.093750

-0.175382

-0.044301

-0.002767

-0.000258

-0.000000

HSP43124