AD9518-3_15 datasheet(10/64 Pages) AD

10 / 64 page

AD9518-3

Data Sheet

Rev. C | Page 10 of 64

SERIAL CONTROL PORT

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

µA

Input Logic 0 Current

110

µA

Input Capacitance

SCLK (INPUT)

SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

110

µA

Input Logic 0 Current

µA

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

1.1

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup and Hold, tS, tH

CS Minimum Pulse Width High, tPWH

PD, SYNC, AND RESET PINS

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

These pins each have a 30 kΩ internal pull-up

resistor

Logic 1 Voltage

2.0

Logic 0 Voltage

0.8

Logic 1 Current

µA

Logic 0 Current

110

µA

Capacitance

RESET TIMING

Pulse Width Low

SYNC TIMING

Pulse Width Low

1.5

High speed

clock cycles

High speed clock is CLK input signal

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