AD9518-3_15 datasheet(50/64 Pages) AD

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AD9518-3

Data Sheet

Rev. C | Page 50 of 64

Reg.

Addr.

(Hex)

Bits

Name

Description

[1:0]

Antibacklash

pulse width

Antibacklash Pulse Width (ns)

2.9 (default); this is the recommended setting, and it does not normally need to be changed

1.3; this setting may be necessary if the PFD frequency > 50 MHz

6.0.

2.9.

0x018

[6:5]

Lock detect

counter

Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked

condition.

PFD Cycles to Determine Lock

5 (default).

16.

64.

255.

Digital lock detect

window

If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock

detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

0: high range (default).

1: low range.

Disable digital

lock detect

Digital lock detect operation.

0: normal lock detect operation (default).

1: disables lock detect.

[2:1]

VCO cal divider

VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.

VCO Calibration Clock Divider

2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.

4. This setting is fine for PFD frequencies < 25 MHz.

8. This setting is fine for PFD frequencies < 50 MHz.

16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.

VCO cal now

Bit used to initiate VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate calibration,

use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if not zero

already), followed by the update all registers bit (Register 0x232, Bit 0); and third, program to 1b, again followed by the

update all registers bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the

PLL losing lock. The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.

0x019

[7:6]

R, A, B counters,

SYNC pin reset

Action

Does nothing on SYNC (default).

Asynchronous reset.

Synchronous reset.

Does nothing on SYNC.

[5:3]

R path delay

R path delay (default = 0x00); see Table 2.

[2:0]

N path delay

N path delay (default = 0x00); see Table 2.

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