4-15

Test Circuit and Waveforms

FIGURE 5. INTERRUPT SIGNAL PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS

FIGURE 6. INPUT MODE TIMING WAVEFORMS

A

1k

Ω

B

1k

Ω

50pF

50pF

A INT

B INT

CDP1851

50%

50%

10%

50%

INPUT

SIGNAL

A, B

VALID PORT ADDRESS

IO OR II

DATA BUS

RA1/RA0

WR/RE = (TPB)

RD/WE = (MRD)

I/O SPACE

RD/WE = (MWR)

WR/RE = (MRD)

MEMORY SPACE

CS

CLOCK = (TPA)

TPB

DATA-IN

STROBE

INT

RDY

CDP1851, CDP1851C