70

Functional Description

The CD22103A is designed to code and decode HDB3

signals which are coded as binary digital signals (NRZ-lN)

and (+HDB3 IN, -HDB3 IN), accompanied by sampling

clocks (CTX) and (CRX). The two binary coded HDB3 out-

puts, (+HDB3 OUT, -HDB3 OUT) may be externally mixed to

create the ternary HDB3 signals (See Figure 1).

The two binary HDB3 input signals have been split from the

input ternary HDB3 in an external line receiver.

The receiver decoder converts binary unipolar inputs (+HDB3 IN,

-HDB3 IN), which were externally split from ternary bipolar HDB3

signals, and a synchronous clock signal (CRX) into binary unipolar

NRZ signals (NRZ-OUT).

Received signals not consistent with HDB3 coding rules are

detected as errors. The receiver error output (ERR) is active high

during one CRX period of each bit of received data that is inconsis-

tent with HDB3 coding rules.

An input string consisting of all ones (or marks) is detected and

signaled by a high level at the Alarm Signal (AIS) output. The AIS

output is set to a high level when less than three zeros are

received during two consecutive periods of the Reset Alarm Inhibit

Signal (RAIS). The AIS output is subsequently reset to a low level

when three or more zeros are received during two periods of the

reset signal (RAIS).

A diagnostic Loop-Test Mode may be entered by driving the Loop

Test Enable Input (LTE) high. In this mode the HDB3 transmitter

outputs (+HDB3 OUT, -HDB3 OUT) are internally connected to

the HDB3 receiver inputs, and the external HDB3 receiver inputs,

and the external HDB3 receiver inputs (+HDB3 IN, -HDB3 IN) are

disabled. The NRZ binary output signal (NRZ - OUT) corresponds

to the NRZ binary input signal (NRZ - IN) delayed by approxi-

mately 8 clock periods.

The Clock Receiver Output (CKR) is the product of the two HDB3

input signals or-ed together. The CRX clock signal may be derived

from the CKR signal with external clock extraction circuitry. In the

Loop Test Mode (LTE = 1) CKR is the product of the +HDB3 OUT

and -HDB3 OUT signals or-ed together.

The CD22103A may also be used to perform the AMI to NRZ

coding/decoding function. To use the CD22103A in this mode, the

HDB3/AMI control input is driven low.

Error Detection

Received HDB3/AMl binary input signals are checked for

coding violations, and an error signal (ERR) is generated as

described below.

• HDB3 Signals HDB3/AMl = High

The error signal (ERR) is flagged high for one CTX period if

a violation pulse (

±V) is received of the same polarity as the

last received violation pulse.

A violation pulse (

±V) is considered a reception error and

does not cause replacement of the last string of 4 bits to

zeros, if:

CRX to CKR (CRX = 8.448MHz)

Pretrigger

5-

-

20

ns

Delay

5-

-

20

ns

DYNAMIC OUTPUT

Transmitter Coder, CTX to HDB3 OUT:

Data Propagation Delay Time

3-

-

90

ns

Handling Delay Time

1

-

4

-

Clock Period

HDB3 OUT Output Pulse Width

(Clock duty cycle = 50%)

3

238

-

260

ns

353

-

65

Receiver Decoder

CRX to NRZ OUT:

Data Propagation Delay Times

4-

-

90

ns

Handling Delay Time

2

-

4

-

Clock Period

HDB3 IN to CKR

HDB3 Propagation Delay Time

LTE = 0

4-

-

65

ns

LTE = 1

4

-

-

30

ns

Electrical Specifications

PARAMETER

SYMBOL

FIGURE

MIN

TYP

MAX

UNITS

CD22103A