DD28F032SA datasheet(16/49 Pages) INTEL

16 / 49 page

DD28F032SA

NOTES:

1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the

actual lock-bit status.

3. A

0 is automatically complemented to load the second byte of data. BYTE# must be at VIL.

The A

0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the

Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page

Buffer expandability.

5. In x16 mode, only the lower byte DQ

0-7 is used for WCL and WCH. The upper byte DQ8-15 is a don’t care.

6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.

9. Program address, PA, is the destination address in the flash array which must match the source address in the Page

Buffer. Refer to the

16-Mbit Flash Product Family User’s Manual.

10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.

11. To ensure that the DD28F032SA’s power consumption during sleep mode reads the deep power-down current level, the

system also needs to de-select the chip by taking either or both CE0# or CE1#/CE2# high.

12. The upper byte of the data bus (DQ8–15) during command programs is a “Don’t Care” in x16 operation of the device.

5.5 Compatible Status Register

WSMS

ESS

DWS

VPPS

654

321

NOTES:

CSR.7 = WRITE STATE MACHINE STATUS

1 = Ready

0 = Busy

RY/BY# output or WSMS bit must be checked to

determine completion of an operation (erase

suspend, block erase or data program) before

the appropriate Status bit (ESS, ES or DWS) is

checked for success.

CSR.6 = ERASE-SUSPEND STATUS

1 = Erase Suspended

0 = Erase In Progress/Completed

CSR.5 = ERASE STATUS

1 = Error in Block Erasure

0 = Successful Block Erase

If DWS and ES are set to “1” during a block

erase attempt, an improper command sequence

was entered. Clear the CSR and attempt the

operation again.

CSR.4 = DATA WRITE STATUS

1 = Error in Data Program

0 = Data Program Successful

CSR.3 = VPP STATUS

1 = VPP Low Detect, Operation Abort

0 = VPP OK

The VPPS bit, unlike an A/D converter, does not

provide continuous indication of VPP level. The

WSM interrogates VPP’s level only after the Data

Program or Block Erase command sequences

have been entered, and informs the system if

VPP has not been switched on. VPPS is not

guaranteed to report accurate feedback between

VPPL and VPPH.

CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS

These bits are reserved for future use; mask them out when polling the CSR.

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