17

AUTOMOTIVE

®

PRODUCT PREVIEW

5.2

Test Conditions: Capacitive load on all pins = 100 pF, rise and fall times = 10 ns, F

XTAL

in clock-doubler mode.

Table 7. AC Characteristics

Symbol

Parameter

Min

Max

Units

The 87C196LB will meet these specifications

F

XTAL

1

Frequency on XTAL1, PLL in 1x mode

8.0

20.0

MHz

(1)

Frequency on XTAL1, PLL in 2x mode

4.0

10.0

f

Operating frequency, f = F

XTAL

8.0

20.0

MHz

Operating frequency, f = 2F

XTAL

mode

t

Period t = 1/f

50

125

ns

T

XHCH

XTAL1 High to CLKOUT High or Low

20

110

ns

(2)

T

CLCL

CLKOUT Cycle Time

2t

ns

T

CHCL

CLKOUT High Period

t – 10

t + 15

ns

T

CLLH

CLKOUT Falling to ALE Rising

– 10

15

ns

T

LLCH

ALE Falling to CLKOUT Rising

– 20

15

ns

T

LHLH

ALE Cycle Time

4t

ns

T

LHLL

ALE High Period

t – 10

t + 10

ns

T

AVLL

Address Setup to ALE Low

t – 15

ns

T

LLAX

Address Hold after ALE Low

t – 40

ns

T

LLRL

ALE Low to RD# Low

t – 30

ns

T

RLCL

RD# Low to CLKOUT Low

4

30

ns

T

RLRH

RD# Low to RD# High

t – 5

ns

T

RHLH

RD# High to ALE Rising

t

t + 25

ns

(3)

T

RLAZ

RD# Low to Address Float

5

ns

T

LLWL

ALE Low to WR# Low

t – 10

ns

T

CLWL

CLKOUT Low to WR# Falling Edge

– 5

25

ns

T

QVWH

Data Valid to WR# High

t – 23

ns

T

CHWH

CLKOUT High to WR# Rising Edge

– 10

15

ns

T

WLWH

WR# Low to WR# High

t – 20

ns

T

WHQX

Data Hold after WR# High

t – 25

ns

NOTES:

1.

Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is only tested

down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz.

2.

Typical specifications, not guaranteed.

3.

Assuming back-to-back bus cycles.

4.

8-bit bus only.