13

AUTOMOTIVE

®

PRODUCT PREVIEW

WR#

O

This active-low output indicates that an external write is occurring. This signal is

asserted only during external memory writes.

Forcing WR# high while RESET# is low, causes the device to enter PLL-bypass

mode. When the device is in PLL-bypass mode, the internal phase clocks

operate at one-half the frequency of the frequency on XTAL1.

WR# shares a package pin with P5.2, WRL#, and PLLEN.

functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects

WRL#.

WRL#

O

During 16-bit bus cycles, this active-low output signal is asserted for low-byte

writes and word writes to external memory. During 8-bit bus cycles, WRL# is

asserted for all write operations.

WRL# shares package pin with P5.2, WR#, and PLLEN.

functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects

WRL#.

XTAL1

I

Input Crystal/Resonator or External Clock Input

Input to the on-chip oscillator and the internal clock generators. The internal

clock generators provide the peripheral clocks, CPU clock, and CLKOUT

signal. When using an external clock source instead of the on-chip oscillator,

connect the clock input to XTAL1. The external clock signal must meet the V

IH

specification for XTAL1.

XTAL2

O

Inverted Output for the Crystal/Resonator

Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design

uses an external clock source instead of the on-chip oscillator.

Table 4. Signal Descriptions (Continued)

Name

Type

Description