80C187

CONTROL WORD

The NPX provides several processing options that are selected by loading a control word from memory into

the control register Figure 5 shows the format and encoding of fields in the control word

Table 2 Condition Code Interpretation

Instruction

C0(S)

C3(Z)

C1(A)

C2(C)

FPREM FPREM1

Three Least Significant

Reduction

(See Table 3)

Bits of Quotient

0 e Complete

Q2

Q0

Q1

1 e Incomplete

or OU

FCOM FCOMP

FCOMPP FTST

Result of Comparison

Zero or

Operand is not

FUCOM FUCOMP

(See Table 4)

OU

Comparable (Table 4)

FUCOMPP FICOM

FICOMP

FXAM

Operand Class

Sign

Operand Class

(See Table 5)

or OU

(Table 5)

FCHS FABS FXCH

FINCSTP FDECSTP

Constant Loads

UNDEFINED

Zero

UNDEFINED

FXTRACT FLD

or OU

FILD FBLD

FSTP (Ext Real)

FIST FBSTP

FRNDINT FST

FSTP FADD FMUL

UNDEFINED

Roundup

UNDEFINED

FDIV FDIVR

or OU

FSUB FSUBR

FSCALE FSQRT

FPATAN F2XM1

FYL2X FYL2XP1

FPTAN FSIN

UNDEFINED

Roundup

Reduction

FCOS FSINCOS

or OU

0 e Complete

Undefined

1 e Incomplete

if C2 e 1

FLDENV FRSTOR

Each Bit Loaded from Memory

FLDCW FSTENV

FSTCW FSTSW

UNDEFINED

FCLEX FINIT

FSAVE

OU

When both IE and SF bits of status word are set indicating a stack exception this bit distinguishes between

Reduction

If FPREM or FPREM1 produces a remainder that is less than the modulus reduction is complete When

reduction is incomplete the value at the top of the stack is a partial remainder which can be used as input to

further reduction For FPTAN FSIN FCOS and FSINCOS the reduction bit is set if the operand at the top of

the stack is too large In this case the original operand remains at the top of the stack

Roundup

When the PE bit of the status word is set this bit indicates whether one was added to the least significant bit of

the result during the last rounding

UNDEFINED Do not rely on finding any specific value in these bits

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