80C187 datasheet(14/30 Pages) INTEL

14 / 30 page

80C187

HARDWARE INTERFACE

In the following description of hardware interface an

overbar above a signal name indicates that the ac-

tive or asserted state occurs when the signal is at a

low voltage When no overbar is present above the

signal name the signal is asserted when at the high

voltage level

Signal Description

In the following signal descriptions the 80C187 pins

are grouped by function as follows

1 Execution Control

CLK CKM RESET

2 NPX Handshake

PEREQ BUSY ERROR

3 Bus Interface Pins

D15–D0 NPWR NPRD

4 ChipPort Select

NPS1 NPS2 CMD0 CMD1

5 Power Supplies

VCC VSS

Table 7 lists every pin by its identifier gives a brief

description of its function and lists some of its char-

acteristics Figure 7 shows the locations of pins on

the CERDIP package while Figure 8 shows the loca-

tions of pins on the PLCC package Table 8 helps to

locate pin identifiers in Figures 7 and 8

Clock (CLK)

This input provides the basic timing for internal oper-

ation This pin does not require MOS-level input it

will operate at either TTL or MOS levels up to the

maximum allowed frequency A minimum frequency

must be provided to keep the internal logic properly

functioning Depending on the signal on CKM the

signal on CLK can be divided by two to produce the

internal clock signal (in which case CLK may be up

to 32 MHz in frequency) or can be used directly (in

which case CLK may be up to 125 MHz)

Clocking Mode (CKM)

This pin is a strapping option When it is strapped to

VCC (HIGH) the CLK input is used directly when

strapped to VSS (LOW) the CLK input is divided by

two to produce the internal clock signal During the

RESET sequence this input must be stable at least

four internal clock cycles (ie CLK clocks when CKM

is HIGH 2 c CLK clocks when CKM is LOW) before

RESET goes LOW

270640 – 5

NC e Pin Not Connected

Figure 7 CERDIP Pin Configuration

270640 – 6

NC e Pin Not Connected

‘‘Top View’’ means as the package is seen from the

component side of the board

Figure 8 PLCC Pin Configuration

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