80960CF-33 datasheet(13/77 Pages) INTEL

13 / 77 page

PRELIMINARY

80960CF-40, -33, -25, -16

BTERM

S(L)

H(Z)

R(Z)

BURST TERMINATE is an input which breaks up a burst access and causes another

address cycle to occur. The BTERM signal works in conjunction with the internally

programmed wait-state generator. If READY and BTERM are enabled in a region, the

BTERM pin is sampled after the programmed number of wait states has expired. When

BTERM is asserted, a new ADS signal is generated and the access is completed. The

READY input is ignored when BTERM is asserted. BTERM must be externally synchro-

nized to satisfy BTERM setup and hold times.

WAIT

H(Z)

R(1)

WAIT indicates internal wait state generator status. WAIT is asserted when wait states

are being caused by the internal wait state generator and not by the READY or BTERM

inputs. WAIT can be used to derive a write-data strobe. WAIT can also be thought of as

a READY output that the processor provides when it is inserting wait states.

BLAST

H(Z)

R(0)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last

data transfer of burst and non-burst accesses after the wait state counter reaches zero.

BLAST remains asserted until the clock following the last cycle of the last data transfer

of a bus access. If the READY or BTERM input is used to extend wait states, the

BLAST signal remains asserted until READY or BTERM terminates the access.

DT/R

H(Z)

R(0)

DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in

conjunction with DEN to provide control for data transceivers attached to the external

bus. When DT/R is asserted, the signal indicates that the processor receives data.

Conversely, when deasserted, the processor sends data. DT/R changes only while

DEN is high.

DEN

H(Z)

R(1)

DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of

the bus request first data cycle and is deasserted at the end of the last data cycle. DEN

is used in conjunction with DT/R to provide control for data transceivers attached to the

external bus. DEN remains asserted for sequential reads from pipelined memory

regions. DEN is deasserted when DT/R changes.

LOCK

H(Z)

R(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK

may be used to prevent external agents from accessing memory which is currently

involved in an atomic operation. LOCK is asserted in the first clock of an atomic opera-

tion and deasserted in the clock cycle following the last bus access for the atomic

operation. To allow the most flexibility for memory system enforcement of locked

accesses, the processor acknowledges a bus hold request when LOCK is asserted.

The processor performs DMA transfers while LOCK is active.

HOLD

S(L)

H(Z)

R(Z)

HOLD REQUEST signals that an external agent requests access to the external bus.

The processor asserts HOLDA after completing the current bus request. HOLD,

HOLDA and BREQ are used together to arbitrate access to the processor’s external

bus by external bus agents.

BOFF

S(L)

H(Z)

R(Z)

BUS BACKOFF, when asserted, suspends the current access and causes the bus pins

to float. When BOFF is deasserted, the ADS signal is asserted on the next clock cycle

and the access is resumed.

Table 2. 80960CF Pin Description — External Bus Signals (Sheet 2 of 3)

Name

Type

Description

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