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28F008C3 датащи(PDF) 35 Page - Intel Corporation |
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28F008C3 датащи(HTML) 35 Page - Intel Corporation |
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35 / 59 page ![]() E 3 VOLT ADVANCED+ BOOT BLOCK 35 PRODUCT PREVIEW 4.8 Reset Operations IH V IL V RP# (P) PLPH t IH V IL V RP# (P) PLPH t (A) Reset during Read Mode Abort Complete PHQV t PHWL t PHEL t PHQV t PHWL t PHEL t (B) Reset during Program or Block Erase, < PLPH t PLRH t PLRH t IH V IL V RP# (P) PLPH t Abort Complete PHQV t PHWL t PHEL t PLRH t Deep Power- Down (C) Reset Program or Block Erase, > PLPH t PLRH t Figure 11. AC Waveform: Reset Operation Table 11. Reset Specifications(1) VCC 2.7V–3.6V Symbol Parameter Notes Min Max Unit tPLPH RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) 2,4 100 ns tPLRH1 RP# Low to Reset during Block Erase 3,4 22 µs tPLRH2 RP# Low to Reset during Program 3,4 12 µs NOTES: 1. See Section 3.1.4 for a full description of these conditions. 2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 3. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. Sampled, but not 100% tested. |
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