28F008C3 datasheet(13/59 Pages) INTEL

13 / 59 page

3 VOLT ADVANCED+ BOOT BLOCK

PRODUCT PREVIEW

3.2.2

READ CONFIGURATION

The

Read

Configuration

mode

outputs

the

manufacturer/device

identifier.

The

device

switched to this

mode

writing

the

Read

Configuration command (90H). Once in this mode,

read cycles from addresses shown in Table 4

retrieve the specified information. To return to read

array mode, write the Read Array command (FFH).

The Read Configuration mode outputs three types

of information: the manufacturer/device identifier,

the block locking status, and the protection register.

The device is switched to this mode by writing the

Read Configuration command (90H). Once in this

mode, read cycles from addresses shown in Table

4 retrieve the specified information. To return to

read array mode, write the Read Array command

(FFH).

Table 4. Read Configuration Table

Item

Address

Data

Manufacturer Code (x16)

00000

0089

Manufacturer Code (x8)

00000

Device ID (See Appendix G)

00001

Block Lock Configuration2

XX002(1)

LOCK

• Block Is Unlocked

DQ0 = 0

• Block Is Locked

DQ0 = 1

• Block Is Locked-Down

DQ1 = 1

Protection Register Lock3

PR-LK

Protection Register (x16)

81-88

Protection Register (x8)

(App. H)

NOTES:

“XX” specifies the block address of lock configuration

being read.

See Section 3.3.4 for valid lock status outputs.

See Section 3.4 for protection register information.

Other locations within the configuration address space

are reserved by Intel for future use.

3.2.3

READ STATUS REGISTER

The status register indicates the status of device

operations,

and

the

success/failure

that

operation.

The

Read

Status

(70H)

command causes subsequent reads to output data

from the status register until another command is

issued. To return to reading from the array, issue a

Read Array (FFH) command.

The status register bits are output on DQ0–DQ7.

The upper byte, DQ8–DQ15, outputs 00H during a

Read Status Register command.

The contents of the status register are latched on

the falling edge of OE# or CE#, whichever occurs

last. This prevents possible bus errors which might

occur if status register contents change while being

read. CE# or OE# must be toggled with each

subsequent status read, or the status register will

not indicate completion of a program or erase

operation.

When the WSM is active, SR.7 will indicate the

status of the WSM; the remaining bits in the status

in performing the desired operation (see Table 7).

3.2.3.1

Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and

clears bits 2, 6 and 7 to “0,” but cannot clear status

bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and

5 indicate various error conditions, these bits can

only be cleared through the use of the Clear Status

software to control the resetting of these bits,

several operations may be performed (such as

cumulatively programming several addresses or

erasing multiple blocks in sequence) before reading

the status register to determine if an error occurred

during that series. Clear the Status Register before

beginning another command or sequence. Note

that the Read Array command must be issued

before data can be read from the memory array.

Resetting the device also clears the status register.

3.2.4

READ QUERY

The Read Query mode outputs Common Flash

Interface (CFI) data when the device is read. This

can be accessed by writing the Read Query

Command (98H). The CFI data structure contains

information such as block size, density, command

set and electrical specifications. Once in this mode,

read cycles from addresses shown in Appendix C

retrieve the specified information. To return to read

array mode, write the Read Array command (FFH).

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