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28F002BC датащи(PDF) 17 Page - Intel Corporation |
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28F002BC датащи(HTML) 17 Page - Intel Corporation |
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17 / 37 page ![]() E 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY 17 PRELIMINARY Erase Resume (D0H) This command will cause the CUI to clear the Suspend state and clear the WSM Status Bit to a “0,” but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect under any other conditions. 3.3.2 STATUS REGISTER The 28F002BC contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status Register command to the CUI. After writing this command, all subsequent read operations output data from the status register until another command is written to the CUI. A Read Array command must be written to the CUI to return to read array mode. The status register bits are output on DQ[0:7]. The contents of the status register are latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. This prevents possible bus errors that might occur if the contents of the status register change while reading the status register. CE# or OE# must be toggled with each subsequent status read to insure the status register is updated; otherwise, the completion of a program or erase operation will not be evident from the status register. When the WSM is active, the status register will indicate the status of the WSM and upon command completion, it will indicate success or failure of the operation (see Table 5 for definition of status register bits). 3.3.2.1 Clearing the Status Register The WSM sets status bits “3” through “7” to “1,” and clears bits “6” and “7” to “0,” but cannot clear status bits “3” through “5” to “0.” Bits 3 through 5 can only be cleared by the controlling CPU through the use of the Clear Status Register command. These bits can indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The status register may then be read to determine if an error occurred during that programming or erasure series. This feature adds flexibility to the way the device may be programmed or erased. To clear the status register, the Clear Status Register command is written to the CUI. Then, any other command may be issued to the CUI. Note, again, that before a read cycle can be initiated, a valid read command must be written to the CUI to specify whether the read data is to come from the memory array, status register, or intelligent identifier. 3.3.3 PROGRAM MODE Programming is executed using a two-write sequence. The Program Setup command is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM then executes a sequence of internally- timed events to: 1. Program the desired bits of the addressed memory byte. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within a byte being changed to a “0.” If the user attempts to program “1”s, there will be no change in memory contents and no error is reported by the status register. Similar to erasure, the status register indicates whether programming is complete. While the program sequence is executing, bit 7 of the status register is a “0.” The status register can be polled by toggling either CE# or OE# to determine when the program sequence is complete. Only the Read Status Register command is valid while programming is active. When programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. If the programming operation was unsuccessful, bit 4 of the status register is set to a “1” to indicate a program failure. If bit 3 is set to a “1,” then VPP was not within acceptable limits, and the WSM did not execute the programming sequence. If the program operation fails, bit 4 of the status register will be set within 1.5 ms, as determined by the timeout of the WSM. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, reads from the memory array cannot be accomplished until the CUI is given the Read Array command. Figure 7 shows the Automated Programming Flowchart. |
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