28F002BC datasheet(13/37 Pages) INTEL

13 / 37 page

28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY

PRELIMINARY

with altering memory contents are accessible via

the CUI.

The purpose of the Write State Machine (WSM) is

to automate the write and erasure of the device

completely. The WSM will begin operation upon

receipt of a signal from the CUI and will report

status back through the status register. The CUI will

handle the WE# interface to the data and address

latches, as well as system software requests for

status while the WSM is in operation.

3.1

Bus Operations

Flash memory reads, erases and writes in-system

via the local CPU. All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles. These bus operations are summarized in

Tables 2 and 4.

3.2

Read Operations

The 28F002BC has three user read modes: read

array, read intelligent identifier, and read status

During power-up conditions, it takes a maximum of

600 ns from when VCC is at 4.5V to when valid data

is available at the outputs.

3.2.1

READ ARRAY

When RP# transitions from VIL (reset) to VIH, the

device will be in read array mode and will respond

to the read control inputs (CE#, OE#, and address

inputs) without any commands being written to the

CUI.

When the device is in read array mode, four control

signals must be manipulated to read data at the

outputs.

• WE# must be logic high (VIH)

• CE# must be logic low (VIL)

• OE# must be logic low (VIL)

• RP# must be logic high (VIH)

In addition, the address of the desired location must

be applied to the address pins. Refer to AC

Characteristics for the exact sequence and timing

of these signals.

If the device is not in read array mode, as would be

the case after a program or erase operation, the

Read Mode command (FFH) must be written to the

CUI before array reads can take place.

Table 2. 28F002BC Bus Operations

Mode

Notes

RP#

CE#

OE#

WE#

VPP

DQ0–7

Read

1,2,3

VIH

VIL

VIH

DOUT

Output Disable

VIH

VIL

VIH

High Z

Standby

VIH

High Z

Deep Power-Down

VIL

High Z

Intelligent Identifier (Mfr)

VIH

VIL

VIH

VID

VIL

89H

Intelligent Identifier (Device)

VIH

VIL

VIH

VID

VIH

7CH

Write

5,6,7

VIH

VIL

VIH

VIL

VPPH

DIN

NOTES:

1. Refer to DC Characteristics.

2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP.

3. See DC Characteristics for VPPLK, VPPH, VHH, VID voltages.

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1-A17 = X.

5. Refer to Table 3 for valid DIN during a write operation.

6. Command writes for program or block erase are only executed when VPP = VPPH.

7. To write or erase the boot block, hold RP# at VHH.

8. RP# must be at GND

± 0.2V to meet the maximum deep power-down current specified.

28F002BC датащи(PDF) 13 Page - Intel Corporation

28F002BC датащи(HTML) 13 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

датащи скачать

ссылки URL