ICS9150-08 datasheet(4/13 Pages) ICST

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ICS9150-08

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence,

with an acknoledge bit between each byte.

The clock generator is a slave/receiver I2C component. It can read back the data stored in the latches for verification. (set

R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the

address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.

The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The

bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte

has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those

two bytes. The data is loaded until a Stop sequence is issued.

G..

At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled

output state).

General I

2C serial interface information

I2C is a trademark of Philips Corporation

Then Byte 0, 1, 2, etc in

sequence until STOP.

Clock Generator

Address (7 bits)

ACK

+ 8 bits dummy

command code

ACK

+ 8 bits dummy

Byte count

ACK

A(6:0) & R/W#

D2(H)

Then Byte 0, 1, 2, etc. in

sequence until STOP.

Clock Generator

Address (7 bits)

ACK

Byte Count

Readback

ACK

A(6:0) & R/W#

D3(H)

Bit

Description

PW D

Bit 7

0 - ±0.25% Spread Spectrum Modulation

1 - ±0.5% Spread Spectrum Modulation

Bit6 Bit5 Bit4

CPU clock

PCI

Note1

Bit 6:4

111

110

100.2

133.32

33.3 (CPU/3)

33.3 (CPU/4)2

101

100

112.02

103

37.3 (CPU/3)2

34.3 (CPU/3)

011

010

66.8

83.3

33.4 (CPU/2)

41.65(CPU/2)

001

000

37.5 (CPU/2)

25 (CPU/2)

Bit 3

0 - Frequency is selected by hardware select, Latched

Inputs

1 - Frequency is selected by Bit 6:4 (above)

Bit 2

0 - Spread Spectrum center spread type.

1 - Spread Spectrum down spread type.

Bit 1

0 - Normal

1 - Spread Spectrum Enabled

Bit 0

0 - Running

1- Tristate all outputs

Note1. Default at Power-up will be for

latched logic inputs to define

frequency. Bits 4, 5, 6 are default

to 000, and if bit 3 is written to a 1

to use Bits 6:4, then these should

be defined to desired frequency at

same write cycle.

Note2. Performance not guaranteed

Note: PWD = Power-Up Default

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