ICS672-01/02

QuadraClock™ Quadrature Delay Buffer

MDS 672-01/02 C

4

Revision 112200

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (note 1)

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD & VDDIO

Referenced to GND

-0.5

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Electrostatic Discharge

MIL-STD-883

2000

V

Ambient Operating Temperature

0

70

°C

Ambient Operating Temperature, Industrial

Available on -02 only

-40

85

°C

Soldering Temperature

Max of 10 seconds

260

°C

Junction temperature

150

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD =VDDIO = 3.3 V unless specified otherwise)

DC CHARACTERISTICS (VDD =VDDIO = 3.3 V unless specified otherwise)

DC CHARACTERISTICS (VDD =VDDIO = 3.3 V unless specified otherwise)

DC CHARACTERISTICS (VDD =VDDIO = 3.3 V unless specified otherwise)

Operating Voltage, VDD

3.13

5.50

V

Operating Voltage, VDDIO

2.375

VDD

V

Input High Voltage, VIH, ICLK only

VDD/2+1

V

Input Low Voltage, VIL, ICLK only

VDD/2-1

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Output High Voltage, VOH

IOH=-12 mA

2.4

V

Output Low Voltage, VOL

IOL=12 mA

0.4

V

Output High Voltage, VOH, CMOS level

IOH=-8mA

VDDIO-0.4

V

Operating Supply Current, IDD (Note 2)

No Load, S1=1, S0=0, S2=0

11

mA

Operating Supply Current, IDD (Note 3)

No Load, S1=1, S0=0, S2=0

22

mA

Short Circuit Current

Each output

±50

mA

Input Capacitance

7

pF

AC CHARACTERISTICS (VDD = VDDIO = 3.3 V unless specified otherwise)

AC CHARACTERISTICS (VDD = VDDIO = 3.3 V unless specified otherwise)

AC CHARACTERISTICS (VDD = VDDIO = 3.3 V unless specified otherwise)

AC CHARACTERISTICS (VDD = VDDIO = 3.3 V unless specified otherwise)

Input Clock Frequency

15

150

MHz

Output Clock Frequency

ICS672-01

15

84

MHz

Output Clock Frequency

ICS672-02

15

135

MHz

Output Clock Rise Time, CL = 15 pF

0.8 to 2.0V

1.5

ns

Output Clock Fall Time, CL = 15 pF

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle, VDDIO=3.3V

At VDDIO/2

45

50

55

%

Phased Outputs Accuracy (Note 4)

rising edges at VDDIO/2

-250

250

ps

Input to Output Skew, ICLK to CLK0 (Note 5)

-300

300

ps

Maximum Absolute Jitter

75

ps

Cycle to Cycle Jitter, 15 pF loads

150

ps

Electrical Specifications

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. With ICLK = 20 MHz, FBCLK to FBIN, all outputs at 40 MHz.

3. With ICLK = 66.5 MHz, FBCLK to FBIN, all outputs at 133 MHz.

4. With CLK0:CLK270 equally loaded, and output frequency > 60 MHz.

5. Rising edge of ICLK compared with rising edge of CLK0, with FBCLK connected to FBIN, 15 pF load on CLK0, and

CLK0 > 60 MHz.