ICS672-01/02

QuadraClock™ Quadrature Delay Buffer

MDS 672-01/02 C

2

Revision 112200

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com

Pin Descriptions

Key: I = Input; O = output; P = power supply connection.

Pin Assignment

ICS672-01/02

External Components

The ICS672-01/01 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between VDD and GND on pins 11 and 12, VDD and GND

on pins 13 and 12, and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series

termination resistor of 33

Ω may be used close to each clock output pin to reduce reflections.

16

15

14

13

16 pin narrow (150 mil) SOIC

12

11

10

9

1

2

3

4

5

6

7

8

CLK90

VDDIO

FBIN

ICLK

CLK270

S0

GND

GND

VDD

GND

S2

S1

VDD

FBCLK

CLK0

CLK180

Number

Name

Type

Description

1

ICLK

I

Clock Input.

2

CLK90

O

Clock Output (90° delayed from CLK0).

3

CLK180

O

Clock Output (180° delayed from CLK0).

4

CLK270

O

Clock Output (270° delayed from CLK0).

5

VDDIO

P

Supply voltage for input and output clocks. Must not exceed VDD.

6, 7, 12

GND

P

Connect to ground.

8

S0

I

Select input 0. See table above.

9

S1

I

Select input 1. See table above.

10

S2

I

Select input 2. See table above.

11, 13

VDD

P

Connect to +3.3 V or +5.0 V.

14

CLK0

O

Clock Output phase aligned to ICLK.

15

FBCLK

O

Feedback Clock Output (0° phase shift from CLK0).

16

FBIN

I

Feedback Clock Input. In normal operation, connect to FBCLK

S2

S1

S0

Output Clocks

0

0

0

Power Down + Tri State

0

0

1

x1

0

1

0

x2

0

1

1

x3

1

0

0

x4

1

0

1

x5

1

1

0

x6

1

1

1

x0.5

Output Clock Mode Select Table