ICS650-12

MPEG Clock Synthesizer

MDS 650-12 A

3

Revision 113000

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (note 1)

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

7

V

Inputs and Clock Outputs

Referenced to GND

-0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 10 seconds

260

°C

Storage temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)

DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)

Operating Voltage, VDD

3.0

5.5

V

Input High Voltage, VIH

2

V

Input Low Voltage, VIL

0.8

V

Output High Voltage, VOH

VDD=3.3V, IOH=-8mA

2.4

V

Output Low Voltage, VOL

VDD=3.3V, IOL=8mA

0.4

V

Output High Voltage, VOH, VDD = 3.3 or 5V

IOH=-8mA

VDD-0.4

V

Operating Supply Current, IDD, at 5V

No Load

39

mA

Operating Supply Current, IDD, at 3.3V

No Load

22

mA

Short Circuit Current, VDD = 3.3 V

Each output

±50

mA

Input Capacitance

Except X1

7

pF

AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)

AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)

Input Crystal or Clock Frequency

27

MHz

Output Clocks Accuracy (synthesis error)

All clocks

0

1

ppm

Output Clock Rise Time

0.8 to 2.0V

1.5

ns

Output Clock Fall Time

2.0 to 0.8V

1.5

ns

Output Clock Duty Cycle

At VDD/2

40

50

60

%

One Sigma Jitter, ACLK

VDD=3.3 V

100

ps

VDD=5.0 V

40

ps

Absolute Clock Period Jitter

VDD=3.3 V, Except CCLK=20 MHz

±300

ps

VDD=5.0 V, Except CCLK=20 MHz

±200

ps

Electrical Specifications

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of

0.01 µF should be connected between VDD and GND on pins 4 and 6, and 16 and 14, and a 33

Ω

terminating resistor may be used on each clock output if the trace is longer than 1 inch.