ICS650-12

MPEG Clock Synthesizer

MDS 650-12 A

2

Revision 113000

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

Pin #

Name

Type

Description

1

PS2

I

Processor Clock Select Pin 2. See above table.

2

X2

XO

Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input

3

X1

XI

Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.

4, 16

VDD

P

Connect to +3.3 V or +5.0 V.

5

CS1

I

Communications Clock Select Pin 1. See above table.

6, 14

GND

P

Connect to ground.

7

ACLK

O

Audio Clock Output. See above table.

8

PCLK1

O

Processor Clock Output 1. See above table.

9

CS0

I

Communications Clock Select 0. See above table.

10

AS2

I

Audio Clock Select Pin 2. See above table.

11

AS0

I

Audio Clock Select Pin 0. See above table.

12

27M

O

27 MHz buffered clock output.

13

13.5M

O

13.5 MHz clock output.

15

AS1

I

Audio Clock Select Pin 1. See above table.

17

PCLK2

O

Processor Clock Output 2. See above table.

18

CCLK

O

Communications Clock Output. See above table.

19

PS0

I

Processor Clock Select Pin 0. See above table.

20

PS1

I

Prcoessor Clock Select Pin 1. See above table.

Pin Descriptions

Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal

connections

1

16

2

3

4

15

14

13

VDD

ACLK

X2

VDD

20 pin SSOP (QSOP)

5

6

7

8

12

11

10

9

AS2

PS0

X1

PS2

CCLK

PS1

PCLK2

27M

AS0

CS0

PCLK1

18

17

19

20

GND

CS1

13.5M

GND

AS1

Pin Assignment

PCLK1 and PCLK2 Select Table (in MHz)

CCLK Select Table (in MHz)

CS1 CS0

CCLK

0

0

All off*

0

1

20.00

1

0

66.6666

1

1

24.576

ACLK Select Table (in MHz)

AS2

AS1

AS0

ACLK

0

0

0

12.288

0

0

1

11.2896

0

1

0

8.192

0

1

1

24.576

1

0

0

8.192

1

0

1

16.9344

1

1

0

18.432

1

1

1

11.2896

PS2

PS1

PS0

PCLK1

PCLK2

0

0

0

108.00

54.00

0

0

1

55.00

27.5

0

1

0

66.67

33.33

0

1

1

80.00

40.00

1

0

0

54.00

27.00

1

0

1

81.00

40.5

1

1

0

50.00

25.00

1

1

1

60.00

30.00

*Note: Entire chip powers

down (outputs stop low)

when CS1 = CS0 = 0.