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ICS1892Y-10 датащи(PDF) 138 Page - Integrated Circuit Systems

номер детали ICS1892Y-10
подробное описание детали  10Base-T/100Base-TX Integrated PHYceiver
PDF  148 Pages
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производитель  ICST [Integrated Circuit Systems]
домашняя страница  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS1892Y-10 датащи(HTML) 138 Page - Integrated Circuit Systems

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ICS1892, Rev. D, 2/26/01
February 26, 2001
138
Chapter 10
DC and AC Operating Conditions
ICS1892 Data Sheet
© 2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
10.5.15
Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion
Table 10-22 lists the significant time periods for the MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins: CRS, COL, and TP_RX (that is, the TP_RXP and
TP_RXN pins). Figure 10-15 shows the timing diagram for the time periods.
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 10-15.
MDI Input to Carrier Assertion / De-Assertion Timing Diagram
Table 10-22.
MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
First Bit of /J/ into TP_RX to CRS
Assert †
–
9
–
13
Bit times
t2
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
Half-Duplex Mode
9
–
13
Bit times
t3
First Bit of /T/ into TP_RX to CRS
De-Assert ‡
–
13
–
17
Bit times
t4
First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
Half-Duplex Mode
–
–
14
Bit times
t1
t2
t3
t4
First bit
First bit of /T/
TP_RX*
*Shown
unscrambled.
CRS
COL



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