ICS1892 datasheet(110/148 Pages) ICST

110 / 148 page

ICS1892, Rev. D, 2/26/01

February 26, 2001

110

Chapter 9

Pin Diagram, Listings, and Descriptions

ICS1892 Data Sheet

MDIO

Input/

Output

Management Data Input/Output.

This pin’s signal is a tri-statable line driven by one of the following:

• Station management (STA), to transfer command information

• The ICS1892, to transfer status information.

All transfers and sampling are synchronous with the signal on the MDC

pin.

Note: If the ICS1892 is to be used in an application that uses the

mechanical MII specification, MDIO must have a 1.5 k

Ω ±5%

pull-up resistor at the ICS1892 end and a 2 k

Ω ±5% pull-down

resistor at the station management end. (These resistors enable

the station management to determine if the connection is intact.)

RXCLK

Receive Clock.

The ICS1892 sources the RXCLK to the MAC/repeater. The ICS1892

uses RXCLK to synchronize the signals on the following pins: RXD0–3,

RXDV, and RXER. The following table contrasts the behavior on the

RXCLK pin when the mode for the ICS1892 is either 10Base-T or

100Base-TX.

Note: The signal on the RXCLK pin is conditioned by RXTRI.

RXD0,

RXD1,

RXD2,

RXD3

35,

34,

33,

Receive Data 0–3.

• RXD0 is the least-significant bit and RXD3 is the most-significant bit of

the MII receive data nibble.

• While the ICS1892 asserts RXDV, the ICS1892 transfers the receive

data signals on the RXD0–RXD3 pins to the MAC/Repeater Interface

synchronously on the rising edges of RXCLK.

Table 9-6.

MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)

Name

Number

Type

Pin Description

10Base-T

100Base-TX

The RXCLK frequency is 2.5 MHz.

The RXCLK frequency is 25 MHz.

The ICS1892 generates RXCLK

from the MDI data stream using a

digital PLL. When the MDI data

stream terminates, the PLL

continues to operate, synchronously

referenced to the last packet

received.

The ICS1892 generates RXCLK

from the MDI data stream while there

is a valid link (that is, either data or

IDLEs). In the absence of a link, the

ICS1892 uses the REFIN clock to

generate the RXCLK.

The ICS1892 switches between

clock sources during the period

between when CRS is being

asserted and RXDV is being

asserted. While the ICS1892 locks

onto the incoming data stream, a

clock phase change of up to 360

degrees can occur.

The ICS1892 switches between

clock sources during the period

between when CRS is being

asserted and RXDV is being

asserted. While the ICS1892 is

bringing up a link, a clock phase

change of up to 360 degrees can

occur.

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