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HMS91C8032 датащи(PDF) 49 Page - Hynix Semiconductor |
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HMS91C8032 датащи(HTML) 49 Page - Hynix Semiconductor |
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49 / 157 page ![]() HMS91C8032/97C8032 46 NOV., 2001 Ver 1.02 Timer/Counter 2 Set-up T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. Figure 4-9 Timer/Counter 2 Control Register (T2CON) Symbol Position Name and Significance (MSB) (LSB) T2CON.7 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ CP/ T2 RL2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. TF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 T2CON.5 Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. RCLK T2CON.4 TCLK Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the transmit clock. T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. EXEN2 T2CON.2 Start/stop control for Timer 2. A logic 1 starts the timer. TR2 T2CON.1 Timer or Counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). C/T2 T2CON.0 Capture/Reload flag. When set, capture will occur on negative transition at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and timer is forced to auto-reload on Timer 2 overflow. CP/RL2 (fCPU/6) RCLK + TCLK CP/ TR2 MODE 0 0 1 16-bit Auto-reload 0 1 1 16-bit Capture 1 X 1 Baud rate generator 1 X 0 (off) Table 4-24 Timer2 Operating Modes RL2 |
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