HMS91C8032 datasheet(27/157 Pages) HYNIX

27 / 157 page

HMS91C8032/97C8032

NOV., 2001 Ver 1.02

INTS0 (RI or TI)

INTT2 (TF2 or EXF2)

INTWDT

INTIFC

INTAD

INTEX2

INTEX3

INTEX4

INTS1

INTS2

INTEX5

INTEX6

INTT3

INTT4

IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE. : B8H

If the bit is 0, the corresponding interrupt has a lower priority and If the bit is 1, the corresponding interrupt has a higher priority.

IP.7

Not implemented, reserved for future use.*

IP.6

Not implemented, reserved for future use.*

IPT2

IP.5

Defines the Timer 2 interrupt priority level

IPS

IP.4

Defines the Serial Port interrupt priority level.

IPT1

IP.3

Defines the Timer 1 interrupt priority level.

IPX1

IP.2

Defines External Interrupt 1 priority level.

IPT0

IP.1

Defines the Timer 0 interrupt priority level.

IPX0

IP.0

Defines the External Interrupt 0 priority level.

* User software should not write 1s to reserved bits. These bits may be used in future DTS3 products to invoke new features. In that case,

the reset or inactive value of the new bit will be 0, and its active value will be 1.

IP2: INTERRUPT PRIORITY REGISTER 2. : B1H

If the bit is 0, the corresponding interrupt has a lower priority and If the bit is 1, the corresponding interrupt has a higher priority.

IP2.7

Not implemented, reserved for future use.*

IP2.6

Not implemented, reserved for future use.*

IP2.5

Not implemented, reserved for future use.*

IPX6

IP2.4

Defines External Interrupt 6 priority level.

IPX5

IP2.3

Defines External Interrupt 5 priority level.

IPX4

IP2.2

Defines External Interrupt 4 priority level.

IPX3

IP2.1

Defines External Interrupt 3 priority level.

IPX2

IP2.0

Defines External Interrupt 2 priority level.

* User software should not write 1s to reserved bits. These bits may be used in future DTS3 products to invoke new features. In that case,

the reset or inactive value of the new bit will be 0, and its active value will be 1.

IPT2

IPS0

IPT1

IPX1

IPT0

IPX0

IPX6

IPX5

IPX4

IPX3

IPX2

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