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Copyright © 2010 Future Technology Devices International Limited

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Document Reference No.: FT_000166

V2DIP2-64 VNCL2-64Q Development Module Datasheet Version 1.01

Clearance No.: FTDI# 155

3.6.2 Timing Diagram – Asynchronous FIFO Mode Read and Write Cycle

When in Asynchronous FIFO interface mode, the timing of a read and write operation on the FIFO

interface is shown in Figure 3.3 and Table 3.7

Figure 3.3 – Asynchronous FIFO Mode Read and Write Cycle.

Time

Description

Min

Max

Unit

t1

RD# inactive to RXF#

1

14

ns

t2

RXF# inactive after RD# cycle

100

-

ns

t3

RD# to Data

1

14

ns

t4

RD# active pulse width

30

-

ns

t5

RD# active after RXF#

0

-

ns

t6

WR# active to TXE# inactive

1

14

ns

t7

TXE# inactive after WR# cycle

100

-

ns

t8

DATA to TXE# active setup time

5

-

ns

t9

DATA hold time after WR# inactive

5

-

ns

t10

WR# active pulse width

30

-

ns

t11

WR# active after TXE#

0

-

ns

Table 3.7 Asynchronous FIFO Mode Read Cycle Timing

In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD#

inputs. In contrast to synchronous mode, in asynchronous mode the 245 FIFO module generates the

output enable EN# signal. EN# signal is effectively the read signal RD#.

Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF#

output will also go high. It will only become low again when there is another byte to read.

When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when

there is still space for data to be written in to the module.