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Copyright © 2010 Future Technology Devices International Limited

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Document Reference No.: FT_000166

V2DIP2-64 VNCL2-64Q Development Module Datasheet Version 1.01

Clearance No.: FTDI# 155

3.5 Serial Peripheral Interface (SPI)

The VNC2-64Q has one master module and two slave modules. These modules are described more fully in

a Vinculum-II datasheet please refer to:- FTDI website

3.5.1 Signal Description - SPI Slave

The SPI Slave signals can be programmed to a choice of available I/O pins. Table 3.4 explains the

available pins for each of the SPI Slave signals.

Available Pins

Name

Type

Description

J2-18, J2-14, J1-17, J1-24, J1-29, J2-

28, J2-23, J1-3, J1-7, J2-8, J2-4

spi_s0_clk

spi_s1_clk

Input

Slave clock input

J2-17, J1-14, J1-18, J1-26, J1-30, J2-

27, J2-22, J1-4, J1-8, J2-7, J2-3

spi_s0_mosi

spi_s1_mosi

Input/Output

Master Out Slave In

Synchronous data from master

to slave

J2-16, J1-15, J1-20, J1-27, J2-30, J2-

26, J1-1, J1-5, J1-9, J2-6, J2-2

spi_s0_miso

spi_s1_miso

Output

Master In Slave Out

Synchronous data from slave to

master

J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,

J1-2, J1-6, J2-9, J2-5, J2-1

spi_s0_cs#

spi_s1_cs#

Input

Slave chip select

Table 3.4 - Data and Control Bus Signal Mode Options – SPI Slave

3.5.2 Signal Description - SPI Master

The SPI Master signals can be programmed to a choice of available I/O pins. Table 3.5 shows the SPI

master signals and the available pins that they can be mapped.

Available Pins

Name

Type

Description

J2-18, J2-14, J1-17, J1-24, J1-29, J2-

28, J2-23, J1-3, J1-7, J2-8, J2-4

spi_m_clk

Output

SPI master clock input

J2-17, J1-14, J1-18, J1-26, J1-30, J2-

27, J2-22, J1-4, J1-8, J2-7, J2-3

spi_m_mosi

Output

Master Out Slave In

Synchronous data from master to

slave

J2-16, J1-15, J1-20, J1-27, J2-30, J2-

26, J1-1, J1-5, J1-9, J2-6, J2-2

spi_m_miso

Input

Master In Slave Out

Synchronous data from slave to

master

J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,

J1-2, J1-6, J2-9, J2-5, J2-1

spi_m_cs_0#

Output

Active low slave select 0 from

master to

slave 0

J2-14, J1-17, J1-24, J1-29, J2-28, J2-

23, J1-3, J1-7, J2-8, J2-4

spi_m_cs_1#

Output

Active low slave select 1 from

master to

slave 1

Table 3.5 - Data and Control Bus Signal Mode Options – SPI Master