L99H01 datasheet(8/53 Pages) STMICROELECTRONICS

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Block diagram and pin description

L99H01

8/53

DocID15567 Rev 6

9CLK

Serial clock input: this input controls the internal shift register of the

SPI and requires CMOS logic levels.This input has a pull-down

current.

Serial data in: the input requires CMOS logic levels and receives serial

data from the microcontroller. The data is an 8-bit control word and the

most significant bit (MSB, bit 7) is transferred first. This input has a

pull-down current.

Serial data out: the diagnosis data is available via the SPI and this

tristate-output. The output remains in tristate, if the chip is not selected

by the input CSN (CSN = high).

12, 14, 19,

20, 22

Not connected.

CSO

Current sense amplifier output: VCC compatible.

CSI1+

Current sense amplifier input: positive input 1, multiplexible.

CSI1-

Current sense amplifier input: negative input 1, multiplexible.

CSI2+

Current sense amplifier input: positive input 2, multiplexible.

CSI2-

Current sense amplifier input: negative input 2, multiplexible.

TS/ ACT_OFF Thermal sensor interface or input to switch all driver active off.

GL2

Gate driver for PowerMOS low-side switch in halfbridge 2.

SL2

Source of low-side switch in halfbridge 2.

GH2

Gate driver for PowerMOS high-side switch in halfbridge 2.

SH2

Source/drain of halfbridge 2.

SL1

Source of low-side switch in halfbridge 1.

GL1

Gate driver for PowerMOS low-side switch in halfbridge 1.

SH1

Source/drain of halfbridge 1.

GH1

Gate driver for PowerMOS high-side switch in halfbridge 1.

Charge pump output.

CP2+

Charge pump pin for capacitor 2, positive side.

CP2-

Charge pump pin for capacitor 2, negative side.

CP1+

Charge pump pin for capacitor 1, positive side.

CP1-

Charge pump pin for capacitor 1, negative side.

Power supply voltage (external reverse protection required).

For EMI reason a ceramic capacitor as close as possible to GND is

recommended.

Table 2. Pin definitions and functions (continued)

Symbol

Function

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