SC3303 datasheet(22/26 Pages) SEMTECH

22 / 26 page

SC3303

Applications Information (continued)

Figure 11 — PCB Layout

SC3303

LX connection

using a Via

FB node

PGND

VESR node

PCB Layout Guidelines

The optimum layout for the SC3303 is shown in Figure 11.

This layout shows an integrated FET buck regulator with a

maximum current of 3A. The total PCB area is approxi-

mately 19.1mm x 11.3mm.

Critical Layout Guidelines

The following critical layout guidelines must be followed

to ensure proper performance of the device.

IC Decoupling capacitors

PGND plane

AGND island

FB and other analog control signals

BST and LX

Capacitors and Current Loops

IC Decoupling Capacitors

A 0.1 μF capacitor must be located as close as

possible to the IC and directly connected to pins

10 (LDO) and 9 (AGND).

All other decoupling capacitors must be located

as close as possible to the IC.

•

PGND Plane

PGND requires its own copper plane with no

other signal traces routed on it.

Copper planes, multiple vias, and wide traces are

needed to connect PGND to input capacitors,

output capacitors, and the PGND pins on the IC.

The PGND copper area between the input

capacitors, output capacitors, and PGND pins

must be as small and compact as possible to

reduce the area of the PCB that is exposed to

noise due to current flow on this node.

Connect PGND to AGND with a short trace or

0Ω resistor. This connection should be as close

to the IC as possible.

AGND Island

AGND should have its own island of copper with

no other signal traces routed on this layer that

connects the AGND pins and pad of the IC to the

analog control components.

All of the components for the analog control cir-

cuitry should be located so that the connections

•

SC3303 датащи(PDF) 22 Page - Semtech Corporation

SC3303 датащи(HTML) 22 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

датащи скачать

ссылки URL