SC3303 datasheet(18/26 Pages) SEMTECH

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SC3303

Applications Information (continued)

Capacitor Selection

The output capacitors are chosen based on required ESR

and capacitance. The maximum ESR requirement is con-

trolled by the output ripple requirement and the DC toler-

ance. The output voltage has a DC value that is equal to

the valley of the output ripple plus 1/2 of the peak-to-peak

ripple. Change in the output ripple voltage will lead to a

change in DC voltage at the output.

The design goal is for the output voltage regulation to be

±4% under static conditions. The internal 750mV reference

tolerance is 1%. Assuming a 1% tolerance from the FB resis-

tor divider, this allows 2% tolerance due to V

OUT

ripple. Since

this 2% error comes from 1/2 of the ripple voltage, the

allowable ripple is 4%, or 132mV for a 3.3V output.

The maximum ripple current of 1.2A creates a ripple

voltage across the ESR. The maximum ESR value allowed

is shown by the following equations.

ESR

RIPPLEMAX

RIPPLE

MAX

203

132

ESR

MAX = 219 mΩ

The output capacitance is chosen to meet transient

requirements. A worst-case load release, from maximum

load to no load at the exact moment when inductor

current is at the peak, determines the required capaci-

tance. If the load release is instantaneous (load changes

from maximum to zero in < 1μs), the output capacitor

must absorb all the inductor’s stored energy. This will

cause a peak voltage on the capacitor according to the

following equation.

OUT

PEAK

RIPPLE

OUT

TOL

MIN

COUT

Assuming a peak voltage V

PEAK

of 3.432 (132mV rise upon

load release), and a 3A load release, the required capaci-

tance is shown by the next equation.

432

203

COUT

MIN

COUT

MIN = 175μF

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 750mV reference, the DL

output is high and the low-side MOSFET is on. During this

time, the voltage across the inductor is approximately V

OUT

This causes a down-slope or falling di/dt in the inductor. If

the load di/dt is not much faster than the di/dt in the

inductor, then the inductor current will tend to track the

falling load current. This will reduce the excess inductive

energy that must be absorbed by the output capacitor,

therefore a smaller capacitance can be used.

The following can be used to calculate the needed capaci-

tance for a given dI

LOAD

/dt. Peak inductor current is shown

by the next equation.

LPK = IMAX + 1/2 x IRIPPLEMAX

LPK = 3A + 1/2 x 2.7A = 3.602A

Current

Load

change

Rate

LOAD

MAX = maximum load release = 3A

OUT

LOAD

MAX

OUT

LPK

TOL

LPK

OUT

Example

LOAD

This causes the output current to move from 3A to 0A in

4.8μs, giving the minimum output capacitance require-

ment shown in the following equation.

OUT

432

602

OUT = 137μF

Note that C

OUT

is much smaller in this example, 137μF

compared to 175μF based on a worst-case load release. To

meet the worst-case design criteria of minimum 137μF,

select three capacitors rated at 47μF and 15mΩ ESR.

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