HT82K68 datasheet(9/40 Pages) HOLTEK

9 / 40 page

Instruction(s)

Table Location

*11

*10

TABRDC [m]

P11 P10

TABRDL [m]

HT82K68E

August 8, 2000

Preliminary

Note: *11~*0: Table location bits

@7~@0: Table location bits

P11~P8: Current program counter bits

Stack register - STACK

This is a special part of the memory which is

used to save the contents of the program coun-

ter (PC) only. The stack is organized into six lev-

els and is neither part of the data nor part of the

program space, and is neither readable nor

writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor

writeable. At a subroutine call or interrupt ac-

knowledgement, the contents of the program

counter are pushed onto the stack. At the end of

a subroutine or an interrupt routine, signaled

by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value

from the stack. After a chip reset, the SP will

point to the top of the stack.

If the stack is full and a non-masked interrupt

takes place, the interrupt request flag will be re-

corded but the acknowledgement will be inhib-

ited. When the stack pointer is decremented (by

RET or RETI), the interrupt will be serviced. This

feature prevents stack overflow allowing the pro-

grammer to use the structure more easily. In a

similar case, if the stack is full and a ²CALL² is

subsequently executed, stack overflow occurs and

the first entry will be lost (only the most recent

four return addresses are stored).

Data memory - RAM

The data memory is designed with 184 ´ 8 bits.

It is divided into two functional groups: special

function registers and general purpose data

memory (160´8). Most of them are read/write,

but some are read only.

The special function registers include the Indi-

rect Addressing register 0 (00H), the Memory

Pointer register 0 (MP0;01H), the Indirect Ad-

dressing register 1 (02H), the Memory Pointer

(ACC;05H), the Program Counter Lower-byte

(TBLP;07H), the Table Higher-order byte regis-

ter (TBLH;08H), the Watchdog Timer option Set-

ting register (WDTS;09H), the Status register

I ndi r e c t A ddr e s s i ng R egi s t er 0

MP 0

I ndi r e c t A ddr e s s i ng R egi s t er 1

MP 1

AC C

PC L

TB L P

TB L H

WD T S

ST A T U S

IN T C

TM R

TM R C

PA C

PB C

PC C

PD C

PE C

G ene r a l P u r p os e

DA T A M E M O R Y

( 160 B y t e s )

S pec i a l P u r pos e

DA T A M E M O R Y

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0A H

0B H

0C H

0D H

0E H

0F H

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1A H

1B H

1C H

1D H

1E H

1F H

FF H

: U nu s ed.

R ead a s ² 00 ²

20H

60H

RAM mapping

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