HT47C20L datasheet(33/55 Pages) HOLTEK

33 / 55 page

HT47C20L

January 18, 2000

Function

RTCC

(09H)

RT0

RT1

RT2

R/W

8 to 1 multiplexer control inputs to select the

real time clock prescaler output

BON

R/W

Voltage low detector enable/disable control bit

²0² indicates voltage detector is disabled

²1² indicates voltage detector is enabled

¾¾

Undefined bit, read as ²unknown²

BLF

Battery low flag

²0² indicates that the voltage is not low

²1² indicates that the voltage is low

6, 7

¾¾

Unused bits, read as ²0²

RTCC Register

Note: ²X² means ²invalid²

Voltage low detector

The HT47C20L provides a voltage low detector

for battery system application. If the battery

voltage is lower than the specified value, the

battery low flag (BLF; bit 5 of RTCC) is set. The

specified value is 1.2V±0.1V. The voltage low

detector circuit can be turn On or Off by writing

a ²1² or a ²0² to BON (bit 3 of RTCC register). A

delay time of 1ms is required to monitor the

BLF after setting the BON bit. The BLF is in-

valid when the BON is cleared as ²0². The volt-

age low detector can be disabled by mask

option.

Buzzer

HT47C20L provides a pair of buzzer output BZ

and BZ, which share pins with PA0 and PA1 re-

spectively, determined by mask option. Its out-

put frequency can also be selected by mask

option.

When the buzzer function is selected, setting

PA.0 and PA.1 ²0² simultaneously will enable

the buzzer output and setting PA.0 ²1² will dis-

able the buzzer output and setting PA.0 ²0² and

PA.1 ²1² will only enable the BZ output and dis-

able the BZ output.

PA1

PA0

Function

(CLR PA.1)

(CLR PA.0)

PA0= BZ

PA1= BZ

(SET PA.1)

(CLR PA.0)

PA0= BZ

PA1= 0

(SET PA.0)

PA0= 0

PA1= 0

Buzzer enable

Programmable frequency divider - PFD

The PFD output shares pin with PA3 as deter-

mined by mask option.

When the PFD option is selected, setting PA3

²0² will enable the PFD output and setting PA3

²1² will disable the PFD output and PA3 output

at low level.

PA3

Function

0 (CLR PA.3)

PA3= PFD Output

1 (SET PA.3)

PA3= 0

PFD output frequency=

timer overflow period

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