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HT1622 датащи(PDF) 8 Page - Holtek Semiconductor Inc

номер детали HT1622
подробное описание детали  RAM Mapping 32x8 LCD Controller for I/O xC
PDF  17 Pages
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производитель  HOLTEK [Holtek Semiconductor Inc]
домашняя страница  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT1622 датащи(HTML) 8 Page - Holtek Semiconductor Inc

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HT1622
8
April 21, 2000
90%
50%
10%
GN D
WR , R D
Cl o c k
t f
t r
t CL K
t CL K
V DD
Figure 1
50%
VA L I D D A T A
50%
DB
W R , R D
Cl o c k
GN D
t su
t h
V DD
V DD
GN D
Figure 2
Functional Description
Display memory - RAM structure
The static display RAM is organized into 64´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be ac-
cessed by the READ, WRITE and
READ-MODIFY-WRITE commands. The fol-
lowing is a mapping from the RAM to the LCD
patterns.
Time base and Watchdog Timer (WDT)
The time base generator and WDT share the
same divided (/256) counter. TIMER
DIS/EN/CLR, WDT DIS/EN/CLR and IRQ
EN/DIS are independent from each other. Once
the WDT time-out occurs, the IRQ pin will re-
main at logic low level until the CLR WDT or
the IRQ DIS command is issued.
SE G 0
SE G 1
SE G 2
SE G 3
SE G 3 1
CO M 4
CO M 5
CO M 6
CO M 7
D3
D2
D1
D0
Da t a
A ddr
63
1
3
5
7
CO M 0
CO M 1
CO M 2
CO M 3
A ddr
62
0
2
4
6
Da t a 4 B i t s
( D3 , D 2 , D 1 , D 0 )
A ddr es s 6 B i t s
( A 5 , A 4 , .... , A 0 )
D3
D2
D1
D0
Da t a
RAM mapping
CS
GN D
50 %
50 %
FI R S T
Cl o c k
LA S T
Cl o c k
GN D
W R , R D
Cl o c k
t su 1
t h1
t CS
V DD
V DD
Figure 3



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