STMPE1801BJR datasheet(31/60 Pages) STMICROELECTRONICS

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STMPE1801

Interrupt system

Doc ID 17884 Rev 3

31/60

9.3

Programming sequence

To configure and initialize the interrupt controller to allow interruption to host, observe the

following steps:

Set the INT_EN_MASK and INT_EN_GPIO_MASK registers to the desired values to

enable the interrupt sources that are to be expected to receive from.

Configure the output interrupt type and polarity and enable the global interrupt mask by

writing to the INT_CTRL.

Wait for interrupt.

Upon receiving an interrupt, the corresponding INT bit is asserted.

The host comes to read the INT_STA register through the I2C interface. A ‘1’ in the

INT_STA bits indicates that the corresponding interrupt source is triggered.

If the IS3 bit in INT_STA register is set, the interrupt is coming from the GPIO controller.

Then, a subsequent read is performed on the INT_STA_GPIO register to obtain the

interrupt status of all 18 GPIOs to locate the GPIO that triggers the interrupt. This is a

‘Hot Key’ feature.

After obtaining the interrupt source that triggers the interrupt, the host performs the

necessary processing and operations related to the interrupt source.

All IS[x] bits in INT_STA register and ISG[x] bits in INT_STA_GPIO register which are

set to ‘1’ prior to the read event are cleared to ‘0’ automatically once the reading of the

registers are completed.

Any interrupt inputs received between reading and auto clearing of the registers are

kept in a shadow register and updated into the INT_STA and INT_STA_GPIO registers

once the auto clearing is completed.

10. Once the interrupt is cleared, the INT pin is also de-asserted if the interrupt type is level

interrupt. An edge interrupt only asserts a pulse width of 200 µs.

11. When the interrupt function is no longer required, the IC0 bit in INT_CTRL may be set

to ‘0’ to disable the global interrupt mask bit.

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