TSB81BA3IPFPEP datasheet(7/58 Pages) TI1

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TSB81BA3EP

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SGLS194A − SEPTEMBER 2003 − REVISED JULY 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

NO.

I/O

DESCRIPTION

AGND

Supply

21, 40, 43,

50, 61, 62

−

Analog circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

AVDD−3.3

Supply

24, 39, 44,

51, 57, 63

−

Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1

µF and 0.001 µF. Lower frequency 10-µF filtering

capacitors are also recommended. These supply terminals are separated from the

PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and DVDD-3.3 terminals internal to the device to

provide noise isolation. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied

together with a low dc impedance connection on the circuit board.

BMODE

CMOS

Beta-mode input. This terminal determines the PHY-link interface connection protocol. When

logic high (asserted), the PHY-link interface complies with the P1394b revision 1.33 standard B

PHY-link interface. When logic low (deassered), the PHY-link interface complies with the legacy

1394a−2000 standard. When using a LLC such as the 1394b TSB82AA2, this terminal must be

pulled high. When using a LLC such as the 1394a−2000 TSB12LV26, this terminal must be tied

low.

NOTE: The PHY-link interface cannot be changed between the different protocols during

operation.

CNA

CMOS

Cable not active output. This terminal is asserted high when there are no ports receiving incoming

bias voltage. When any port receives bias, this terminal goes low.

CPS

CMOS

Cable power status input. This terminal is normally connected to cable power through a 400-k

Ω

resistor. This circuit drives an internal comparator that detects the presence of cable power. This

transition from cable power sensed to cable power not sensed may be used to generate an

interrupt to the LLC.

CTL0

CTL1

CMOS

I/O

Control I/Os. These bidirectional signals control communication between the TSB81BA3 and the

LLC. Bus holders are built into these terminals.

D0−D7

CMOS

11, 12, 13,

15, 16, 17,

19, 20

I/O

Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus holders

are built into these terminals.

DGND

Supply

4, 14, 38,

64, 72, 76

Digital circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

DS0

CMOS

Data-strobe-only mode for port 0. 1394a-only port 0 enable programming terminal. On hardware

reset, this terminal allows the user to select whether port 0 acts like a 1394b bilingual port (terminal

at logic 0) or as a 1394a−2000-only port (terminal at logic 1). Programming is accomplished by

tying the terminal low through a 1-k

Ω or less resistor (to enable 1394b bilingual mode) or high

through a 1-k

Ω or less resistor (to enable 1394a−2000-only mode). A bus holder is built into this

terminal.

DS1

CMOS

Data-strobe-only mode for port 1. 1394a-only port 1 enable programming terminal. On hardware

reset, this terminal allows the user to select whether port 1 acts like a 1394b bilingual port (terminal

at logic 0) or as a 1394a−2000-only port (terminal at logic 1). Programming is accomplished by

tying the terminal low through a 1-k

Ω or less resistor (to enable 1394b bilingual mode) or high

through a 1-k

Ω or less resistor (to enable 1394a−2000-only mode). A bus holder is built into this

terminal.

DVDD-CORE

Supply

8, 37, 65,

−

Digital 1.95-V circuit power terminals. A combination of high-frequency decoupling capacitors

near each terminal are suggested, such as paralleled 0.1

µF and 0.001 µF. An additional 1-µF

capacitor is required for voltage regulation. These supply terminals are separated from the

DVDD-3.3, PLLVDD-CORE, PLLVDD-3.3, and AVDD-3.3 terminals internal to the device to

provide noise isolation.

DVDD-3.3

Supply

6, 18, 69,

−

Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near

each terminal are suggested, such as paralleled 0.1

µF and 0.001 µF. Lower frequency 10-µF

filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a

low-impedance point on the circuit board. These supply terminals are separated from the

PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and AVDD-3.3 terminals internal to the device to

provide noise isolation. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied

together with a low dc impedance connection on the circuit board.

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