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AT25DF512C

DS-25DF512C–030A–4/2014

12.7

Hold

The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock

sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program

or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the

erase cycle will continue until it is finished.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the

HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won’t be

started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin

and CS pin are asserted.

While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be

ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If

the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning of the next SCK

low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be

aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.

Figure 12-8. Hold Mode

12.8

Reset

In some applications, it may be necessary to prematurely terminate a program or erase operation rather than wait the

hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. The

Reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle

state. Since the need to reset the device is immediate, the Write Enable command does not need to be issued prior to the

Reset command. Therefore, the Reset command operates independently of the state of the WEL bit in the Status

Register.

The Reset command can be executed only if the command has been enabled by setting the Reset Enabled (RSTE) bit in

the Status Register to a Logical 1 using write status register byte 2 command 31h. This command should be entered

before a program command is entered. If the Reset command has not been enabled (the RSTE bit is in the Logical 0

state), then any attempts at executing the Reset command will be ignored.

To perform a Reset, the CS pin must first be asserted, and then the opcode F0h must be clocked into the device. No

address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the device immediately after the

opcode. Any additional data clocked into the device after the confirmation byte will be ignored. When the CS pin is

deasserted, the program operation currently in progress will be terminated within a time of t

erase operation may not complete before the device is reset, the contents of the page being programmed or erased

cannot be guaranteed to be valid.

SCK

CS

HOLD

Hold

Hold

Hold